完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
大家好!
我一直在处理我的Spartan 3A版本的问题。 JTAG似乎不起作用。 我注意到TDO似乎很高。 它需要大约300欧姆才能将其拉低到足以将其注册为逻辑0,因此我不认为它只是拉高了。 它好像在被驱使? 我也不认为它与Vcc短路,因为导轨很好但是使用非常低值的电阻可以将该引脚上的电压拉低。 我还检查并重新检查了六次以确保物理上,所有JTAG引脚都连接到FPGA上的正确引脚。 我确定他们是。 这提出了防止边界扫描,设备ID检测等工作的问题。 (旁注:有没有办法让iMPACT程序通过TDI作为测试,看看TDO是否坏了?) 我不认为FPGA本身是砖块,因为我可以看到INIT_B引脚的反应不同,具体取决于模式引脚的设置。 当设置为JTAG配置模式时,即使PROG_B保持低电平,INIT_B引脚也会变为高电平。 这让我很奇怪,但是当我测试主SPI模式时,我注意到它的表现不同。 在再次走低之前,INIT_B会在短时间内走高。 这可能表示存储器中的CRC错误是预期的,因为存储器是空的。 这似乎表明某种逻辑正在发挥作用。 什么可能出错? 这是非常令人困惑的,因为它是我的第一个“从头开始”项目 - 我一直使用开发板。 如果我做错了或设备坏了,很难说。 以上来自于谷歌翻译 以下为原文 Hello, folks! I've been dealing with a problem on a Spartan 3A build of mine. JTAG doesn't appear to work. I've noticed that TDO seems to stick high. It takes about 300 ohms to pull it low enough to register as a logical zero, so I don't believe it's just pulled high. It seems to be being driven? I also don't think it's shorted to Vcc since the rails are fine but the voltage on that pin can be pulled low using a very low value resistor. I've also checked and re-checked probably six times to make sure that physically, all the JTAG pins are connected to the correct pins on the FPGA. I'm certain they are. This presents a problem that prevents a boundary scan, device ID detection, etc from working. (Side note: Is there a way to have iMPACT program over TDI anyway as a test to see if just TDO is broken?) I don't think the FPGA itself is a brick since I can see that the INIT_B pin reacts differently depending on what the Mode pins are set to. When set to JTAG config mode, the INIT_B pin goes high even if I have PROG_B held low. It struck me as odd, but when I tested master SPI mode I noted that it behaved differently. INIT_B would go high for a short moment before going low again. This probably indicates a CRC error in the memory which is expected since the memory is empty. That seems to indicate that some sort of logic is working. Any ideas on what might be going wrong? This is very confusing since it's my first "from scratch" project--I've used development boards until now. Hard to say if I'm doing something wrong or if the device is broken. |
|
相关推荐
6个回答
|
|
从我能看到的内容看,原理图看起来很干净。
有明显的事情 检查任何新的董事会。 布局是否与原理图匹配? 是部分 正确焊接在板上? 你说有“非常僵硬”的上拉 JTAG线。 确保没有将它们短接在一起或与其他短路 附近的针脚(至少你没有使用BGA,所以你可以用这些 即使你需要一台显微镜来看你正在做什么,事情也会发生。 - Gabor - Gabor 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 The schematic looks pretty clean from what I can see. There are the obvious things to check with any new board. Does the layout match the schematic? Is the part properly soldered on the board? You said there were "pretty stiff" pullups on the JTAG lines. Make sure you don't have them shorted together or to other nearby pins (at least you're not working with a BGA so you can ohm these things out even if you need a microscope to see what you're doing). -- Gabor -- GaborView solution in original post |
|
|
|
如果您在未配置FPGA的情况下遇到JTAG问题(DONE引脚=低电平),则会出现电路板设计(或汇编)问题。
您可以随时发布您的电路板原理图以供审核。 你建立了多少板,它们的行为是否相同? 您的电源轨电压测量值是多少? 我不认为FPGA本身就是砖块,因为我可以看到INIT_B 引脚的反应取决于模式引脚的设置。 当设置为JTAG配置模式时,INIT_B引脚即使有,也会变为高电平 PROG_B保持低位。 正常。 INIT_B将在PROG_B脉冲上脉冲为低电平,然后变为高电平并保持高电平直到配置数据出现问题。 在发生一些JTAG数据问题之前,INIT_B将保持高位。 这让我很奇怪,但是当我测试主SPI模式时 我注意到它的表现不同。 INIT_B会短暂走高 再次走低之前的那一刻。 这可能表示CRC错误 内存空的预期内存。 正确。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 If you have JTAG problems with the FPGA unconfigured (DONE pin = LOW), then you have a board design (or assembly) problem.
I don't think the FPGA itself is a brick since I can see that the INIT_B pin reacts differently depending on what the Mode pins are set to. When set to JTAG config mode, the INIT_B pin goes high even if I have PROG_B held low.Normal. INIT_B will pulse low on PROG_B pulse, then go high and stay high until a config data problem. Until some JTAG data problem occurs, INIT_B will stay high. It struck me as odd, but when I tested master SPI mode I noted that it behaved differently. INIT_B would go high for a short moment before going low again. This probably indicates a CRC error in the memory which is expected since the memory is empty.Correct. - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
要使JTAG工作,需求很少:
任何影响JTAG或上电复位的银行的Vccint和Vcco(取决于FPGA系列) PROGB(必须高 - 不能重置) TDI TMS TCK:检查这些连接是否尽可能靠近FPGA引脚 确保你真的用Impact驱动它们。 我认为TDO很高是违约的 JTAG复位状态,因此不计时TCK可能会导致您的问题。 模式引脚不应影响JTAG操作。 HTH, 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 For JTAG to work there are very few requirements: Vccint and Vcco for any bank that affects JTAG or power-on reset (depends on FPGA family) PROGB (must be high - out of reset) TDI TMS TCK: Check connections to these as close as possible to the FPGA pins to make sure you're really driving them with Impact. I think high on TDO is default for a JTAG reset state, so not clocking TCK might cause your issue for example. Mode pins should not affect JTAG operation. HTH, Gabor -- Gabor |
|
|
|
|
|
|
|
从我能看到的内容看,原理图看起来很干净。
有明显的事情 检查任何新的董事会。 布局是否与原理图匹配? 是部分 正确焊接在板上? 你说有“非常僵硬”的上拉 JTAG线。 确保没有将它们短接在一起或与其他短路 附近的针脚(至少你没有使用BGA,所以你可以用这些 即使你需要一台显微镜来看你正在做什么,事情也会发生。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 The schematic looks pretty clean from what I can see. There are the obvious things to check with any new board. Does the layout match the schematic? Is the part properly soldered on the board? You said there were "pretty stiff" pullups on the JTAG lines. Make sure you don't have them shorted together or to other nearby pins (at least you're not working with a BGA so you can ohm these things out even if you need a microscope to see what you're doing). -- Gabor -- Gabor |
|
|
|
圣洁的。
有时候这是简单的事情,你知道吗? 我打破了数字万用表,开始测试不良焊点的引脚,当我意识到整个右半部分(引脚51到100)被镜像连接时,你的建议是什么。 针51被视为100,52被视为99,53被视为98,依此类推。 难怪它不起作用。 让我们再试一次,好吗? :) 我是这样的新手! 但是,嘿,无论如何它很有趣。 毕竟,这就是测试板的用途。 这是一个很简单的错误。 FPGA通过DIP分线卡与电路板的其余部分连接。 通过不重新开始第二行底部的编号而不是顶部的编号,这是一个简单的标记问题。 以上来自于谷歌翻译 以下为原文 Holy crud. Some times it's the simple things, you know? I broke out the DMM to start testing pins for bad solder joints and what not as you'd suggested when I realized that the entire right half (pins 51 to 100) were wired up mirrored. Pin 51 was being treated as 100, 52 as 99, 53 as 98, and so on. No wonder it didn't work. Let's try this one again, shall we? :) I'm such a novice! But hey, it's fun anyway. This is what test boards are for, after all. It's a simple enough mistake to make. The FPGA interfaces with the rest of the board via a DIP breakout card. It was a simple matter of bad marking by not restarting the numbering at the bottom of the second row instead of the top. |
|
|
|
只有小组成员才能发言,加入小组>>
2322 浏览 7 评论
2734 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2217 浏览 9 评论
3295 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2369 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
656浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
463浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
225浏览 1评论
669浏览 0评论
1864浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-10-1 18:04 , Processed in 1.243244 second(s), Total 89, Slave 71 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号