在xc3s1000中多少个时钟周期相乘？

Spartan 3中的18位有符号乘法器是组合的。
表现将限于
数据表中注明的延迟路径。
基本上，如果您在一个时钟周期上应用输入，
只要时钟很慢，输出就会在同一个时钟周期内有效
足够。
所以大多数情况下的答案是尽可能快地运行
在寄存器之前放置一个寄存器，在乘法器之后放置另一个寄存器以避免任
LUT延迟。
然后数据表编号可以帮助您估算最大时钟
速度你可以运行它们。
用输入和看看整个包裹的乘数
输出寄存器在配置为最快时钟时似乎需要两个周期
速度。
如果您的时钟要求更加宽松，您可以摆脱其中一个或两个
寄存器并以1个时钟或无时钟延迟结束。
希望这不会让人感到困惑，
的Gabor
-  Gabor



以下为原文

The 18-bit signed multipliers in Spartan 3 are combinatorial.  Performance will be limited to
the delay paths noted in the data sheet.  Basically if you apply inputs on one clock cycle,
then the outputs will be valid during the same clock cycle as long as your clock is slow
enough.  So the answer for most cases, is that to run as quickly as possible you should
place a register before and another register after the multipliers to avoid any other
LUT delays.  Then the datasheet numbers can help you to estimate the maximum clock
speed you can run them at.  Looking at the whole wrapped multiplier with input and
output registers it appears to take two cycles when configured for the fastest clock
speed.  If your clock requirements are more relaxed you can get rid of one or both
registers and end up with 1 clock or no clock latency.
 
Hope this is not more confusing,
Gabor
-- Gabor

总而言之。
对于DSP模块，有更多的TAP，时钟可以更快。



以下为原文

In one word. for the DSP block, more TAPs there are, faster the clock can be.

你好
这里没人回答！
在这种情况下，我发现在ISE中敲响快速测试设计很有用。
尝试使用核心向导，然后将设计放入一个代表芯片。
合成，看看你得到什么速度，



以下为原文

Hi
 
a none answer here !
 
In cases like this, I find it useful to knock up a quick test design in ISE.
 
try using the core wizard, and then put design into a representetive chip.
 
synthesis, and see what speed you get ,