可以使用USB连接将数据发送到PC吗？

简答：不。
更长的回答：也许，但这是很多工作。
Xilinx没有设计Spartan 3E入门套件，其目的是将电缆用于专有的Xilinx JTAG下载电缆以外的任何其他产品。
他们显然采用了标准的USB下载线设计，并将固有的“远端”逻辑从电缆本身移到了电路板上，以节省资金，但电气方面也是如此。
专有的Xilinx电缆在远端有一个来自赛普拉斯的USB从芯片，该芯片位于Spartan 3E入门套件板上。
请注意，电路板的这一部分未记录在原理图或用户手册中。
该芯片有一个USB从机和一个8051微处理器。
微处理器运行代码，实现专有的Xilinx协议以执行下载。
在尝试使WebPack与非标准Linux发行版和版本一起工作时，实验者在确定当前的“包装器”方法之前采取了几种方法。
一种方法涉及在柏树设备中重新编程8051以运行开放协议。
开发人员认为，通过少量的额外工作，可以建立从FPGA到PC的数据路径。
有关开发人员页面的链接，请参阅http://gentoo-wiki.com/HOWTO_Xilinx，“Xup：Spartan 3e入门套件的GPL程序员”部分。
开发人员的想法是对CPLD进行编程（也不在原理图上），以便从8051的一些FPGA IO引脚打开一条漂亮的简单数据路径。
如果这太可怕了，另一种方法是注意使用JTAG引脚必须已经存在可用路径，因为Chipscope（显然）使用这种方法。
我花了大约一个小时考虑这一点，并得出结论，实现以太网接口会更容易。



以下为原文

Short answer: no.  Longer answer: maybe, but  it's a lot of work.
 
Xilinx did not design the Spartan 3E starter kit with the the intention of using the cable for anything other than a proprietary Xilinx JTAG download cable. They apparently took their standard USB download cable design and moved the proprietay "far end" logic from the cable itself onto the board, to save money, but electrically it is the same.  The proprietary Xilinx cable has a USB slave chip from Cypress at the far end, and this chip is on the Spartan 3E starter kit board. Note that this portion of the board is not documented on the schematic or in the user manual.
 
The chip has a USB slave and a 8051 microprocessor. The microprocessor runs code that implements a proprietary Xilinx protocol to perform the downloads.
 
While attempting to get the WebPack to work with non-standard Linux distributions and versions, experimenters took several approaches before settling on the current "wrapper" approach. One approach involved reprogramming the 8051 in the cypress device to run an open protocol. The developer opined that with a small amount of extra work, it would be possible to establish a data path from the FPGA to the PC.
 
See http://gentoo-wiki.com/HOWTO_Xilinx , section  "Xup: GPL programmer for Spartan 3e Starter Kit" for links to the developer's page.
 
The developer's idea was to perhaps program the CPLD (also not on the schematic) to  open a nice simple data path from the 8051 some FPGA IO pins. If this is too frightening, an alternative is to note that there must already be a usable path using the JTAG pins, because Chipscope (apparently) uses this approach. 
 
I spent about an hour thinking about this and concluded that it will be easier to implement an Ethernet interfce. 

您将如何实现以太网接口？
我有一个CoolRunner-II演示板，正在看以太网模块：
http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,822&Prod=PMOD-NIC
我需要在PC上使用什么样的软件才能读取数据？
谢谢
埃里克



以下为原文

 

How would you implement an Ethernet interface?

I have a CoolRunner-II demoboard, and am looking at the Ethernet module:

http://digilentinc.com/Products/Detail.cfm?NavPath=2,401,822&Prod=PMOD-NIC

What kinda software would I need on the PC to read the data?

Thanks

Eric