输入的Vref限制？

假设Spartan 6申请，对吧？
VREF在一组IO标准的背景下列在数据表中，具有小的（非常小的，通过TTL / CMOS标准）逻辑摆幅，因此噪声容限很小。
这是需要专用VREF电源以获得可接受的噪声容限和抗噪声能力的地方。
如果数据表中缺少特定枚举应用程序之外的目的，那么您可能会从遗漏中谨慎地得出一些推论：
1.不支持除数据表中明确列举的应用程序之外的应用程序。
2.未对数据表中未明确列举的性能和特性进行测试（更不用说保证）。
3.数据表中未明确列举的性能和特性如有更改，恕不另行通知。
鉴于四比较器的成本为12美分，您如何向项目经理证明您将设计置于风险之中以节省成本？
不要忘记LM339a四比较器具有比Spartan-6 FPGA（用作比较器）的差分输入更多*更好的模拟量规格。
底线：
对于高速数字，请使用Spartan 6输入。
对于精密模拟，请使用离散比较器。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Assume Spartan 6 application, right?
 
VREF is listed in the datasheet in the context of a set of IO standards with small (very small, by TTL/CMOS standards) logic swings and consequently small noise margins.  This is where a dedicated VREF supply is required for acceptable noise margin and noise immunity.  If purposes beyond the specific enumerated applications are missing from the datasheet, there are some inferences which you might prudently draw from the omission:
 
1.  Applications other than those specifically enumerated in the datasheet are not supported.
2.  Performance and characteristics not specifically enumerated in the datasheet are not tested (much less guaranteed).
3.  Performance and characteristics not specifically enumerated in the datasheet are subject to change without warning.
 
Given that a quad comparator costs 12 cents, how might you justify to your project manager that you put the design at risk to save so little cost?  Don't forget that a LM339a quad comparator has *much* better analogue specs than the differential inputs of a Spartan-6 FPGA (used as a comparator).
 
Bottom line:
For high-speed digital, go with the Spartan 6 inputs.  For precision analogue, go with discrete comparator.
 
-- Bob Elkind
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当然，但我正在寻找为高速数字构建运行时可调电路，从噪声中挖掘出质量差的数字输入，而不知道电路板构建时的电平是多少。
Spartan-6输入可以在部分重新配置的数据表使用中做到这一点，但这很麻烦而且没有很大的灵活性（特别是当涉及到极少摆动的信号时）。
LM339a是......好吧，我确实说过“快”。
而LM339a在现代数字信号方面并不快，但如果您认为我要求的是模拟解决方案，那么这不是一个不合理的选择。
有些比较器可以快速轻松地连接到Spartan-6（例如AD8465），但每个输入的电路板价格为3美元和几平方厘米，因此存在一些严格的实施限制。
有更便宜和更小的路径来获得输入比较器，但如果片上版本可用一些警告，那将更好。
我理解数据表的局限性。
显然，任何这种用法都会带来您描述的风险，需要在Xilinx现成的产品之外进行表征和测试。
我希望来自Xilinx的有实施知识的人可以提供更多的指导 - 无可否认无法提供IP的保证或细节 - 关于输入比较器如何在硅片中实现以及在什么情况下（如果有的话）他们肯定会
停止表现为数字比较器。



以下为原文

Sure, but I'm looking to build a runtime tunable circuit for high-speed digital, to dig poor-quality digital inputs out of the noise without knowing at board-build time what the levels will be.  The Spartan-6 inputs can maybe do that within datasheet usage with partial reconfiguration, but that's a lot of hassle and not a lot of flexibility (particularly when it comes to signals that arrive with very little swing).
 
The LM339a is ... well, I did say "fast".  And I the LM339a is not fast in terms of modern digital signaling, though if what you thought I was asking for was an analog solution, then it's not an unreasonable choice.
 
There are comparators that are fast and easy to connect to a Spartan-6 (AD8465, for instance), but at $3 and several cm^2 of board per input, there are some severe implementation constraints to deal with there.  There are cheaper and smaller routes to getting input comparators, but if on-chip versions were available with some caveats, that would be a lot better.
 
I understand the limitations of the datasheet.  Clearly any usage of this sort runs the risks you describe and requires characterization and testing outside what is provided by Xilinx off the shelf.  My hope was that someone from Xilinx with knowledge of the implementation could provide more guidance -- admittedly without guarantees or specifics that would reveal IP -- on how the input comparators are implemented in the silicon and under what circumstances (if any) they will definitely stop behaving as a digital comparator.
 
 

众所周知，Xilinx使用不同的晶圆厂并“旋转”掩膜组以优化产品成本（我认为低产品成本是一个有价值的特性）。
出于这个原因（除了之前描述的原因，您似乎很清楚），除非您计划对零件进行生产筛选，否则第三方设备特性或测试不是一种防弹措施。
出于您所描述的目的，一个简单（且便宜）的数字电位器难道不会提供您想要的所有逻辑参考电压可编程性吗？
您甚至可以使用LM431电压基准来获得温度和电压抗扰度。
如果你想要数字输入的速度，那么就有很多高速差分接收器（与比较器相比），成本非常低。
如果您非常关注模拟属性（例如特性或测试），那么现成的接收器可能比Xilinx FPGA更容易（也更便宜）来源，特性，规格，屏幕和测试。
你打算增加滞后吗？
流氓数字输入是否具有单调边缘？
多少噪音？
等等
不幸的是，没有免费的午餐。
不过，有很多便宜的替代品，你听起来像一个非常聪明和精明的设计师。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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你读过手册了吗？
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以下为原文

Xilinx is known to use different fabs and to "spin" mask sets to optimise product cost (and I consider low product cost a valuable feature) .  For this reason (in addition to the previously described reasons, of which you seem to be well aware), unless you plan on production screening of parts, 3rd party device characterisation or testing is a less than bulletproof approach.
 
For the purposes you describe, wouldn't a simple (and cheap) digital potentiometer provide all the logic reference voltage programmability you desire?  You could even throw in an LM431 voltage reference for temperature and voltage immunity.
 
If you want speed for digital inputs, there are plenty of high-speed differential receivers (vs. comparators) around, for very little cost.  If you are so concerned about analogue attributes (e.g. characterisation or testing), off-the-shelf receivers would likely be much easier (and cheaper!) to source, characterise, spec, screen, and test than a Xilinx FPGA.
 
Are you planning on adding hysteresis?  Do the rogue digital inputs have monotonic edges?   How much noise?  etc. etc.
 
There's no free lunch, unfortunately.  There are plenty of cheap alternatives, though, and you sound like a pretty clever and astute designer.
 
-- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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谢谢你的想法。
是的，我认为这涵盖了我正在考虑的设计范围 - 你对于面具转速是正确的，并且在产品生命周期的中途只是发现Xilinx不再使特定的转速有效...这是一个
非首发。
差分接收器非常好 - 不幸的是我主要是空间和功率受限，所以片上会非常棒......但我同意你的看法，除非Xilinx愿意提供更多，否则这里可能有太多变量。
我暗地希望会有一个我忽略的应用笔记，这将使这一切都清楚。
今天尝试免费（或至少是非常小的PCB房地产）午餐。
:)



以下为原文

Thanks for the thoughts.  Yeah, I think that covers the range of designs I was considering -- you're right about the mask revs, though, and getting halfway through the product lifetime only to find Xilinx no longer makes the specific rev that works ... that's a non-starter.
 
Differential receivers are very good -- unfortunately I'm primarily space and power constrained, so on-chip would be really great ... but I agree with you that unless Xilinx is willing to provide more, there are probably too many variables here.  I was secretly hoping there would be an app note I had overlooked that would make this all clear.
 
So much for today's attempt at a free (or at least very small PCB real estate) lunch. :)

你愿意放弃吗？
您还没有告诉我们您的应用程序的最低规格是什么...
速度/带宽
2.逻辑摆幅/噪声抗扰度
边缘率
Xilinx确实提供了差分接收器规范，它们并非完全“紧密”（出于可以理解的原因）。
你能忍受什么，以及什么打破了这笔交易？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Are you ready to give up?  You haven't told us what the minimum specs are for your application...
 
1.  speed/bandwidth
2.  logic swing/noise immunity
3.  edge rate
 
Xilinx does provide diff receiver specs, they simply aren't all that "tight" (for understandable reasons).  What can you live with, and what breaks the deal?
 
-- Bob Elkind
SIGNATURE:
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Summary:
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2. Search the forums (and search the web) for similar topics.
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精密比较器的内部是匹配的晶体管对。
在digikey.com的快速扫描中，我发现SC70.6封装的250MHz Ft NPN匹配对大约4.3美分。
一对额外的Rs和一个电流源（npn + R）将这一对转变为CML（ECL的前体）比较器。
便宜，小巧，快捷。
您可以通过SPICE模拟其中的鼻涕来调整速度与功率与电压范围的关系。
如果需要更多电压摆幅，请添加NPN跟随器。
也许这给你一些思考的东西......
1.快
2.精确
3.低功率
A.板载差分接收器：1 + 3
B. LM339：2 + 3
C.高速比较器：1 + 2
你明白了......
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

The guts of an exquisite comparator is a matched transistor pair.  In a quick scan of digikey.com, I found a 250MHz Ft NPN matched pair in SC70.6 package for around 4.3 cents.  A couple of extra Rs and a current source (npn + R) turns this pair into a CML (precursor to ECL) comparator.   Cheap, small, and fast.
 
You get to SPICE simulate the snot out of it to tweak speed vs. power vs. Voltage range.
 
Add an NPN follower if you need more voltage swing.
 
Maybe this gives you something to think about...
 
1.  FAST
2.  PRECISE
3.  LOW POWER


A.  onboard diff receiver:  1+3
B.  LM339:                  2+3
C.  hi-speed comparator:    1+2
 
You get the idea...
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗯，问题是输入可能是一个相当广泛的事情 - 没有太多的细节（不想激怒我们的公司IP类型），我没有控制或发射机的精确规格。
或者更准确地说，有数百种发射器规格可供支持），因此信号可以以不同的摆幅和电平到达。
我认为在比较器阈值附近我们不需要大的滞后电平，因此可以找到VILmax和VIHmin之间几百毫伏的比较器型输入。
对于干净，良好端接的信号，带宽需要至少为750Mb / s，这将取代使用Virtex-II上的标准Xilinx LVCMOS输入获得500Mb / s的设备。
我的目标是将该设计更新为更新的FPGA，提高每引脚带宽，并使标准PCB组件能够补偿更多的外部变送器变化，而无需硬件定制。
Spartan-6上的IODELAY区块在这方面非常出色，但我希望在级别方面更加灵活。
看起来Xilinx差分接收器具有良好的共模范围，但~1V最大差分电压（VID）将成为问题。
我可以对输入进行电阻分压以满足VID规范，但是灵敏度会比我想要的更多。
Spartan-6数据表确实为SSTL3输入列出了这个：
* VIL：-0.5分钟，最大VREF-0.1
* VIH：VREF + 0.1分钟，最大4.1
这将是完美的，除了它还分别列出了VREF的最小值和最大值1.3和1.7。
如果Xilinx列出VREF最小值/最大值仅表示输入在这些VREF情况下符合JEDEC SSTL3，但SSTL3输入VIL / VIH规格仍然适用于更广泛的VREF范围，那么我将全部设置。
在这种配置中只有VREF范围（比方说）0.5-2.0几乎可以解决我的问题。
我可以将IO缓冲区重新配置为SSTL3，SSTL2，HSTL_18等，以降低VREF的范围，但如果VREF不高于1.7，我无法补偿想要为0-3.3V的信号，但结果有点高
（输入是过压钳位，所以我只需要在电路的这一部分调整阈值，以恢复时钟到数据的时序余量...这是一个时钟转发的总线数据输入设置，我想我
之前没有说过）。
似乎通过宽共模外部LVDS接收器（类似于FIN1108）方法的比较器更灵活，除非我可以更自由地假设有关SREL / HSTL的VREF。



以下为原文

Well, the problem is that the inputs could be a fairly wide range of things -- without going into too much detail (don't want to anger our corporate IP types), I don't have control or precise specification for the transmitter.  Or perhaps more accurately, there are hundreds of transmitter specs to support), so the signals can arrive with varying swing and levels.  I don't think we need large levels of hysteresis around the comparator threshold, so comparator-type inputs with a few hundred millivolts between VILmax and VIHmin is find.  Bandwidth needs to be at least 750Mb/s for clean, well-terminated signals, this is replacing equipment that gets 500Mb/s using standard Xilinx LVCMOS inputs on Virtex-II.  My goal is to update that design to a newer FPGA, improve per-pin bandwidth, and have the standard PCB assembly compensate for more external transmitter variation without requiring hardware customization.  The IODELAY blocks on Spartan-6 are fantastic in this regard, but I would like to be more flexible about levels as well.
 
It looks like the Xilinx differential receivers have a decent common-mode range, but the ~1V max differential voltage (VID) would be a problem.  I could resistively divide the input to meet the VID spec, but then sensitivity suffers more than I would like.
 
The Spartan-6 datasheet does list this for the SSTL3 input:
 * VIL: -0.5 min, VREF-0.1 max
 * VIH: VREF+0.1 min, 4.1 max
 
which would be perfect, except that it also lists a min and max for VREF of 1.3 and 1.7, respectively.  If Xilinx lists the VREF min/max only to say that the inputs are compliant with JEDEC SSTL3 under those VREF circumstances, but the SSTL3 input VIL/VIH specs still apply over a much wider VREF range, then I would be all set.  Just having a VREF range of (say) 0.5-2.0 in this configuration would pretty much solve my problem.  I could reconfigure the IO buffers to SSTL3, SSTL2, HSTL_18, etc to step down the range of VREF, but without a VREF above 1.7 I can't compensate for a signal that wanted to be 0-3.3V but ended up a bit higher (inputs are over-voltage clipped, so I just need to adjust the threshold in this portion of the circuit to recover things like clock-to-data timing margin ... this is a clock-forwarded bussed data input setup, I guess I didn't say that before).
 
It seems like comparators via a wide-common-mode external LVDS receiver (something like FIN1108) approach is more flexible unless I can be more liberal with assumptions about VREF with SSTL/HSTL.