怎么将FPGA与接口连接起来

看看下面的免费培训：
http://www.xilinx.com/training/free-video-courses.htm#DSP
您还可以从以下主题中找到SysGen参考文档：
http://forums.xilinx.com/t5/DSP-Tools/Available-System-Generator-Documentation/m-p/52551
干杯，吉姆



以下为原文

Take a look at the free training below:
 
http://www.xilinx.com/training/free-video-courses.htm#DSP
 
Also you can find SysGen reference documents from the thread below:
 
http://forums.xilinx.com/t5/DSP-Tools/Available-System-Generator-Documentation/m-p/52551
 
Cheers,
Jim

嗨，
sysgen的循环选项中有一个硬件，但它只适用于一些特殊的（昂贵的）电路板。
我们的学生最近制作了一个简单的硬件测试平台，通过RS232连接（因此存在关于速度的瓶颈），但基本上可以用它测试几乎任何IP核（源或网表）。
它由带有UART的Picoblaze和连接到DUT（IP-Core）的端口组成。
PicoBlaze软件与matlab通信。
已经编写了一些函数来设置刺激并接收响应。
使用matlab / simulink，您可以使用多种方法将其嵌入到simulink模型中并执行扩展模拟。
此外，您是否已经使用过Sysgen的HDL-Cosimulation功能？
为此，您将HDL-Design放入“黑盒子”符号中，然后Simulink控制HDL模拟器，它能够让您更深入地了解设计中发生的事情，而不是硬件测试台。
你只能检查输入与输出。
但是模拟器也可以向您显示任何内部信号的状态。
有一个很好的模拟
Eilert



以下为原文

Hi,
there is a hardware in the loop option for sysgen, but it only works with some special (costly) boards.
 
Our students recently made a  simple hardware testbench that's connected via RS232 (so there's a bottleneck concerning  speed) but  basically one can test almost any IP-core (source or netlist) with it.
It consists of a Picoblaze with a UART and ports connected to the DUT (IP-Core).
The PicoBlaze software communicates with matlab. Some functions have been written to set stimuli and receive the responses.
With matlab/simulink you have several methods to embed this into a simulink model and perform extended simulations.
 
Besides, have you already used the HDL-Cosimulation features of Sysgen?
For that you put your HDL-Design in a "Black Box" Symbol, and Simulink then controls the HDL Simulator, which is capable to give you much more insight to the things that happen inside your design, than a Hardware Testbench can. Ther you can only check inputs vs. outputs. But a simulator can show you the state of any internal signal too.
 
Have a nice simulation
 Eilert

谢谢eilert和jimwu，
我没有尝试过SysGen的HDL协同仿真功能。
如果可能的话，你可以给我发送任何可以帮助我进行设计的教程的链接。



以下为原文

Thanks eilert and jimwu,
 
I haven't tried HDL cosimulation features of SysGen. If possible could you send me  links to any such tutorial that could help me in my design.

嗨，
请参阅sysgen用户指南。
特别是关于“导入HDL模块”的章节及其子章节。
有趣的是它出现在关于HW协同仿真的部分之后。
有一个很好的模拟 
Eilert



以下为原文

Hi,
see the sysgen user guide.
especially the chapter about "Importing HDL Modules" and it's subchapters.
Funny that it comes after the part about HW-cosimulation.
 
Have a nice simulation
  Eilert