如何同步2个时钟

R，
您没有提供足够的信息来提供答案：
这些钟表在哪里？
他们来自哪里？
你能调整它们吗？
2.这些时钟是异步的，等时的还是合成的？
如果您不知道这些术语的含义：请查看它们，以便您了解它们。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

r,
 
You have not provided enough information to supply an answer:
 
1.  Where are these clocks?  Where do they come from?  Are you able to adjust them?
 
2.  Are these clocks asynchronous, isochronous, or syntonous?  If you do not know what these terms mean:  go look them up, so you understand them.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

其中一个时钟是顶部模块的输入（频率f）。
另一个是由频率8f＆amp;频率的外部时钟（到顶部模块）产生的。
使用DCM_SP除以4以获得2f的输出clkdv。
我需要同步f＆amp;
2f时钟。
不，我不能仅使用DCM来乘以它们，因为它们低于DCM的最小输入频率。
我猜这意味着他们是异步的......
谢谢。



以下为原文

One of the clocks is an input (freq f) to the top module.
 
The other is generated from an external clock (to the top module) of freq 8f & divided by 4 using DCM_SP to get a output clkdv of 2f.
 
I need to synch the f & 2f clocks. No, I couldn't use DCM just to multiply since they fall way below the min input freq of the DCM.
 
I guess that means they're asynchronous.. 
 
Thanks.

R，
是否有数据与您需要发送到设备（和进程）的外部时钟对齐，或者设备中是否有数据需要发送出去，并与外部时钟对齐？
如果是这种情况（或两者兼而有之），那就是FIFO用于：将数据从一个时钟域传输到另一个时钟域。
使用FIFO时，有数据可以告诉您何时可以读取或写入数据。
当FIFO已满时，它会告诉您它不能再保存数据（直到有人从另一端读出一些数据）。
当FIFO为空时，您需要等到另一方输入内容。
在您的情况下，FIFO需要是异步的，您会发现已经内置到硬件（V5，V6）中，或者库中有“IP核”来执行此操作，或者您可能会写
您自己的FIFO的HDL代码（虽然不建议这样做，除非您已经知道自己在做什么）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

r,
 
Is there data aligned with the external clock that you need to send into the device (and process), or is there data in the device, which needs to be sent out, and aligned with the external clock?
 
If this is the case (either, or both), that is what a FIFO is used for:  to transfer data from one clock domain, to another.
 
When using a FIFO, there are flags to tell you when data is ready to be read, or written.  When the FIFO is full, it will tell you that it can hold no more data (until someone reads some out the other end).  When the FIFO is empty, you will need to wait until the other side puts something in.
 
 The FIFO in your case, needs to be an asynchronous one, and you will find that either already built into the hardware (V5, V6), or there are "IP cores" in the libraries to do this, or you may wiish to write the HDL code for your own FIFO (although this is not recommended, unless you already know what you are doing).
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose