使用1800A-DSP实现一个状态机来加载配置为3M x 32的6 x IS61WV102416 SRAM存储器件可行吗

快速思考，
这些存储器设备，“芯片”（即单个负载）或每个都有许多芯片的模块（即多负载）？
以72 Mhz驱动6个负载并非不可能，请检查设备上的定时性能时钟。
但
驱动6'负载会产生长的痕迹，如果你可以有两个独立的总线，每个有三个负载，更好，路由更好，更快。
注意SSL，即银行允许一次切换多少输出。 
这取决于设备，速度，银行以及您使用的标准。



以下为原文

Quick thought,
 
are these memory devices, 'chips' ( i.e. single load ) or modules each with many chips on them ( i.e. multi load ) ?
 
 
Driving 6 loads at 72 Mhz is not beyond impossible, check timing performance clock to out on the device.
 but
Driving 6 'load's is going to give long ish traces, better if you can to have two separate bus each with three loads, should route better, and faster. 
 
Watch out for the SSL, i.e. how many outputs on a bank are allowed to switch at once.
  It depends upon the device, the speed, the bank and what Io standard you are using.
 
 

非常感谢。这些设备都是单独的1M x 16而不是模块。
你所建议看的是我的主要关注点，所以有了更多的阅读，我应该对它的工作更有信心。再次感谢回复巴里威所有人必须从某个地方开始！



以下为原文

Thanks for that. 

The devices are all individual 1M x 16 and not on a module. What you have suggested looking at were my main concerns as well so with a bit more reading I should have a bit more confidence about it working. 
Thanks again for reply

Barry

we all have to start somewhere!

嗨巴里， 
关于这一点只是一些想法。
您可能需要考虑使用同步SRAM而不是异步。
一。
用异步。
SRAM，你
需要记住的是，您的总访问时间是地址线的时钟输出时间+ SRAM的访问时间+电线延迟+
使用驱动访问的时钟在FPGA中捕获数据所需的设置时间。
新的内存接口可能会相当混乱
到FPGA设计:-)。 
同步SRAM通常是流水线的，因此访问在多个时钟周期内被分解。
您的吞吐量保持不变，但是
延迟增加（仅2或3个周期）。
就你的逻辑而言，你只需在特定的时钟周期发出你的读取请求......你会
我知道数据可以在几个周期之后被捕获。
此外，如果您布置电路板使所有信号都跟踪匹配，
您可以使用FPGA中的一个功能来扭曲存储器的时钟，从而实际上消除延迟，从而使您的存储器接口更加强大。
那里
还可以使用其他功能，具体取决于FPGA如何通过对所用内存的重新计时来实现。 
另一件事......如果你需要在writedata到达时准备你的记忆（即你的记忆内容随着时间的推移而变化），那么它可能是可能的
使用同步RAM要容易一些，因为您可以更轻松地安排所有交易（即将它们排队并将它们计时）。
当你
必须驱动异步。
RAM，实际上，您必须自己创建此同步层。 
对不起，如果我在这里混淆。
虽然是异步的。
记忆将工作得很好，只是可能会有一些隐藏的陷阱会让你感到沮丧
你是这个东西的新手:-)。
同步方法将有助于缓解其中一些问题。
大多数同步RAM可能会花费更多，但我认为
如果设计不是非常*成本很有意义，那么这是一个更好的设计决策。
埃德



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Hi Barry,
 
   Just a few thoughts on this.  You might want to consider using a synchronous SRAM as opposed to an async. one.  With async. SRAM, you
need to keep in mind that your total access time is the clock-to-out of your address lines + the access time of the SRAM + the wire delays + the
setup time required to capture data in the FPGA using the clock that drives the access.  Memory interfacing can get fairly confusing when new
to FPGA design :-). 
 
   Synchronous SRAMs are typically pipelined, so the access is broken up on multiple clock cycles.  Your throughput stays about the same, but
there is an increase in latency (only 2 or 3 cycles).  In terms of your logic, you'd simply issue your read request on a particular clock cycles...you'd
know that data would be available for capture a couple of cycles later.  Moreover, if you layout your board such that all of your signals are trace matched,
you could use a feature in the FPGA to skew the memory's clock to virtually remove delays thus making your memory interface a heck of a lot more robust.  There
are also other features you can use depending on how your FPGA is clocked with resepct to the memory being used.
 
   One other thing....if you need to read your memory while write data is arriving (i.e. the contents of your memory is going to change over time), it would proabably
be a bit easier to use a synchronous RAM since you can schedule all of your transactions a bit easier (i.e. queue them up and clock them out).  When you
have to drive an async. RAM, you, in effect, have to create this synchronization layer yourself. 
 
   Sorry if I am being confusing here.  While an async. memory will work just fine, its just that there might be a few hidden gotchas that will frustrate you if
you are new to this stuff :-).  A synchronous approach will help to alleviate some of these issues.  Most synchronous RAMs may cost a bit more, but I think it
is a better design decision if the design is not *extremely* cost concious. 
 
Ed

嗨Ed和其他人，
感谢您的投入，非常感谢。
我将再看看Sync SRAM解决方案，但我认为功能将会很大。
另外，你对PISice转换的IBIS有什么了解吗？
我正在尝试研究如何使用一个名为IBIS2SPICE翻译器的程序并且有点卡住了。
在翻译了Ibis文件（Xilinx 1800-A-DSP）之后，Pspice给了我几个模型，我不知道如何连接在一起，这些包括，我想翻译的实际输出加上电源，gnd，上拉和拉
-down pspice模型。
大多数这些型号至少有4个引脚，但没有迹象表明它们的功能。
如果你或任何其他可能会阅读此内容的人可以提供帮助，我的头可以不再受到伤害而不会撞到墙上。
问候
巴里



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Hi Ed and others,
 
Thanks for the input, it is very much appreciated. I will have a look again at the Sync SRAM solution but I think the power will be to much. On another note, do you know anything about IBIS to Pspice conversion. I'm trying to work out how to use a program called IBIS2SPICE translator and are a bit stuck. After translating the Ibis file (Xilinx 1800-A-DSP) Pspice gives me several models that I'm not sure how to connect together, these include, the actual output I want to translate plus a power, gnd, pull-up and pull-down pspice model. Most of these models have at least 4 pins but there is no indication to what function they perform.
If you, or anybody else who may read this can help, my head can stop hurting from banging it against a wall.
 
Regards
 
Barry