I2C核心问题浮动SCL线

您是否看过您的焊盘报告以确保SCL引脚位于右侧引脚上？
如果SCL定义为内部上拉，则不需要减少SCL
外部电阻。
如果它被弱化，那就不是软件问题了
配置后，上拉或下拉不会改变。
另一件事
尝试生成网表，默认IOB设置为拉起而不是下拉。
如果这改变了行为，则不会在正确的引脚上获得SCL。
-  Gabor
在原帖中查看解决方案



以下为原文

Did you look at your pad report to make SURE that the SCL pin is on the right pin?
 
If your SCL is defined with an internal pullup, you should not need to reduce your
external resistor.  If it is getting pulled down weakly, it is not a software issue,as
the pullup or pulldown does not change after configuration.  Another thing to
try is to generate the netlist with the default IOB set to pull up instead of down.
If this changes the behavior you are not getting SCL on the right pin.
-- GaborView solution in original post

由于你有一个2.2K电阻到3.3V，我建议SCL线是
实际上并非“浮动”而是微弱地拉下来。
是否有可能
内核是否已将引脚配置为下拉或保持器？
您可以在FPGA编辑器中进行检查。
-  Gabor



以下为原文

Since you have a 2.2K resistor to 3.3V, I would suggest that the SCL line is
not actually "floating" but rather weakly pulled down.  Is it possible that the
core has caused the pin to be configured with a pull-down or keeper?
 
You can check this in the FPGA editor.
-- Gabor

好吧，我在ISE中看到SCL也被配置为3.3V的上拉和硬件以及单独的（固件中的硬件和引脚）。
它没有任何帮助。
同样的问题不断发生。



以下为原文

Well, I looked in ISE en configured SCL also as a Pull-up to 3.3V and in hardware and also seperatly (hardware and pin in firmware). It doesn't help anything. the same problem keeps occuring.

另一件事也可以在FPGA编辑器中看到。
确保您的SCL引脚未从设计中移除或
搬到另一个别针。
未使用的IOB的默认操作是添加
下拉电阻，可能会导致您看到的症状。
如果来自核心的名称没有，SCL可以移动到不同的引脚
例如，匹配.ucf文件中的引脚名称。
问候，
的Gabor
-  Gabor



以下为原文

One other thing which may also be seen in the FPGA editor.
 
Make sure that your SCL pin has not been removed from the design or
moved to another pin.  The default action for unused IOB's is to add
a pulldown resistor, which could cause the symptoms you are seeing.
 
SCL could move to a different pin if the name from the core does not
match the pin name in your .ucf file for example.
 
Regards,
Gabor
-- Gabor

你好Gabor，
我真的很感谢你帮助我！
但问题还没有解决！
我查看了我的.ucf文件，这是正确的。
名称（包括capitel Letters）是100％相同。
引脚也连接到它。
我用200欧姆减小了电阻，现在电压电平足够高，以便从机对应时钟信号。
但这不是解决方案，因为只有浮动电平更高（0.2V）。
我不认为这是硬件问题，而是MCBR寄存器的设置或其他东西（在初始时间内是从属的核心？）。
你能告诉我如何设置这个寄存器来执行作为主人的操作吗？
1件事是我不看任何中断信号，我只想通过总线作为主设备发送数据，并将从设备数据作为主设备（我正在连接DS1631 temp.sens。）。
我可以看到SDA线是正确的，并正确拉到3.3V。
再次感谢你的帮助！
射线
消息由404278编辑于01-15-2009 06:52 AM



以下为原文

Hello Gabor,
I really appreciate you help me! But the problem isn't fixed yet!
I looked in my .ucf file and that is correct. The name (including capitel Letters) is 100% the same. Also the pin i connected it to.
 
I reduced my resistor with 200 ohms and now the voltage level is high enough for the slave to correspond on the clock signal. But that's not the solution, because only the floating level is higher (0.2V). I don't think it's a hardware problem but the settings of the MCBR registers or something (is the core a slave in initial time?). Can you tell me how to set this register to perform actions as a master?
 
1 thing is that i don't look at any interrupt signals, i just want to send data over the bus as a master, and gate the slave data as a master (I'm interfaceing a DS1631 temp.sens.).
I can see the SDA line is correct and is correctly pulled op to 3.3V. 
 
Thanks again for your help!
 
Ray
Message Edited by 404278 on  01-15-2009 06:52 AM

您是否看过您的焊盘报告以确保SCL引脚位于右侧引脚上？
如果SCL定义为内部上拉，则不需要减少SCL
外部电阻。
如果它被弱化，那就不是软件问题了
配置后，上拉或下拉不会改变。
另一件事
尝试生成网表，默认IOB设置为拉起而不是下拉。
如果这改变了行为，则不会在正确的引脚上获得SCL。
-  Gabor



以下为原文

Did you look at your pad report to make SURE that the SCL pin is on the right pin?
 
If your SCL is defined with an internal pullup, you should not need to reduce your
external resistor.  If it is getting pulled down weakly, it is not a software issue,as
the pullup or pulldown does not change after configuration.  Another thing to
try is to generate the netlist with the default IOB set to pull up instead of down.
If this changes the behavior you are not getting SCL on the right pin.
-- Gabor

嗨Gabor，
感谢您的信息！
我解决了问题！
该线路连接到我未在.ucf中定义的输入引脚。
那个针被拉下来了。
所以你是对的！
这是硬件！
日Thnx
射线



以下为原文

Hi Gabor,
 
Thanks for the information! I got the problem solved! The line was connected to an input pin i didn't define in the .ucf. That pin was pulled down. So you were right!
It was hardware!
 
thnx
Ray