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我正在开发一个用于模拟传感应用的PCB。它在PSoC3上使用12位Delta Sigma ADC。像往常一样,应用程序非常受空间限制(11mm×21mm),所以我不得不在PCB版图上做出一些妥协,而我不会在更大的PCB上这样做。
该板是由规定6V,并包含两个5V线性稳压器。用于数字电源的MCP1702和模拟电源的MIC5205。该板感测五个A1324霍尔效应传感器。每个霍尔效应输出信号由100NF+1K RC滤波器滤波。一个传感器在PCB本身(右下角)。另4个插头插入右手6针连接器。芯片是一个SPI从机,但是ADC采样总是在SPI事务之间进行,所以SPI不应该干扰模拟信号。可悲的是,我仍然看到一些噪音(大约1.5 LSB在12位)上的模拟信号,我不知道是否有什么我可以做不同的(在布局或其他方面),以改善它。 我用MC2308完成的其他PCB设计,和相同的双5V电源,相同的传感器,和相同的RC滤波器在12位没有达到明显的噪声。我真的想把它推向12 eNoB。原因不是准确度,而是速度测量。目前,这种噪声水平使得机器人无法进行精确的位置和速度控制。 PNG 127.2 K 以上来自于百度翻译 以下为原文 I am developing a PCB for an analogue sensing application. It uses the 12-bit Delta Sigma ADC on a PSoC3. As usual, the application is very space constrained (11mm x 21mm), so I have had to make some compromises in the PCB layout which I would not have done on a larger PCB. The board is supplied by regulated 6v, and contains two 5v linear regulators. An MCP1702 for the digital supply, and an MIC5205 for the analogue supply. The board is sensing five A1324 Hall effect sensors. Each Hall effect output signal is filtered by a 100nF + 1k RC filter. One sensor is on the PCB itself (bottom right). The other 4 plug into the right hand 6-pin connector. The chip is acting as an SPI slave, but ADC samples are always taken between SPI transactions, so the SPI should not interfere with the analogue signals. Sadly, I am still seeing some noise (about 1.5 LSB at 12-bits) on the analogue signals, and I wonder if there is anything I could have done differently (in the layout or otherwise) to improve it. Other PCB designs I have done using the MCP2308, and the same dual 5v supplies, same sensors, and same RC filters have achieved no noticeable noise at 12 bits. I would really like to push it towards 12 ENOB. The reason is not accuracy, but velocity measurement. Currently this level of noise is making it impossible to do accurate position and velocity control on a robot.
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6个回答
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在5 V系统中,12V,1/2 LSB=6 mV。在我看来,任何5磅的LSB都很好。
在混合信号设计中。一种观察噪声的方法PK PK是无穷大的。 坚持,观察供应轨道。 你可以看看监管机构的PSRR和Nosie规格,在一个12位的系统中,它们可能是 意义重大。您使用的帽子也是类型。 一些有用的参考文献 HTTP//TEFCHATICES/KEMET/RESPLATE MNO2-具有导电聚合的钽电容器。896049269845 513555 8467 3020828 ANY355.PDF HTTP://www. CyPress?COM/?RID=39677 问候,Dana。 全AtoD Error.zip 12.1兆字节 以上来自于百度翻译 以下为原文 In a 5 V system, 12V, 1/2 l*** = ~ .6 mV. In my opinion anything < 5 LSBs pretty good in a mixed signal design. One method of looking at noise, pk-pk, is scope on infinite persistance, and watch the supply rails. You might look at PSRR and nosie specs on regulators, in a 12 bit system they may be significant. Also type of caps you are using. Some useful references - http://www.newark.com/pdfs/techarticles/kemet/Replacing-MnO2-with-Conductive-Polymer-in-Tantalum-Capacitors.pdf http://www.analog.com/static/imported-files/application_notes/294542582256114777959693992461771205AN280.pdf http://www.analog.com/static/imported-files/application_notes/6001142869552014948960492698455131755584673020828AN_345.pdf http://www.cypress.com/?rID=39677 Regards, Dana.
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5 LSB?如果我有5磅的噪音,我会认为这是一场彻底的灾难!
然而,在布局上有什么可以影响S/N的东西吗? 以上来自于百度翻译 以下为原文 5 LSB?! If I got 5 LSB of noise I would consider that to be a complete disaster! Nevertheless, is there anything you can see on the layout that might be affecting the S/N ? |
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另外,如果PSoC不能期望达到10.5以上的ENOB,为什么有些有16位ADC?
16位ADC是否只有1.5 LSB噪声,因此达到14.5 eNB? 以上来自于百度翻译 以下为原文 Also, if a PSoC can't be expected to achieve more than 10.5 ENOB, why do some have a 16-bit ADC? Will a 16-bit ADC have only 1.5LSB noise, and therefore achieve 14.5 ENOB? |
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我认为达纳的意思是“5个数”,它更像是2.5位。假设1位意味着0.6MV,这将是一个大约3MV的噪声。
以上来自于百度翻译 以下为原文 I think dana meant '5 counts', which is more like 2.5 bits. Given that 1 bit means 0.6mV, this would be a noise of about 3mV. |
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哦,关于你原来的问题:有AppNONE AN56821-PSOC3和PSOC5混合信号电路板布局考虑(HTTP://wwwyCysP.COM/)?RID=39677)应该对你有帮助。它解释了即使是20位的性能也需要什么。
(很难从图像中分辨出来,因为我们看不见组件,但是我猜你没有把PSoC电源和接地信号分成一个数字和模拟域。这意味着负载的变化会在这些信号上引入噪声电压尖峰,并且在地面上它们对精度是致命的。 以上来自于百度翻译 以下为原文 Oh, and regarding your original question: there is AppNote AN57821 - PSoC3 and PSoC5 Mixed Signal Circuit Board Layout Considerations ( http://www.cypress.com/?rID=39677 ) which should help you. It explains what is needed for achievinbg even 20bits performance. (Its difficult to tell from the image, since one cannot see the components, but I would guess you didn't separate the PSoC supply and the ground signals into a digital and a analog domain. This would mean that changes in the load introduce noise voltage spikes on these signals - and on ground they are deadly for precision) |
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我的意思是5个LSB。如果你看一个典型的董事会环境,
通常你会看到200至400 mV的噪音供应轨,如果你 不要分开A和D场地,在一个入口点把它们放在一起, 在董事会的边缘,你在自找麻烦。 它不是PSoC问题,而是一个系统问题。有多少人能结束 设计中的噪声、偏移、温度、PSRR、热预算。除此之外,我几乎没有 测试世界的HPS和Tektronix和Marconis。实际看多少 C ESR曲线和SPICE模拟电力环境?这是我个人的信仰 很多东西都放在那里,上面写着“我有20个比特”,但是到处都找不到。 噪声和实际的精度和漂移。这是因为当你尝试做一个完整的12位时, 1/2 LSB超过所有错误和温度和V,你突然发现实际上有多困难 是。 看一下聚合物帽,它们是一个数量级更好的ESR vs F。 散装需要。而C在V上的表现要好得多。 问候,Dana。 以上来自于百度翻译 以下为原文 I actually meant 5 l***s. If you look at a typical board environment, often you will see 200 - 400 mV noise on supply rail, and if you do not separate A and D grounds, joing them at a single point of entry, at board edge, you are asking for trouble. Its not a PSOC issue, its a system issue. How many people do an end to end noise, offset, temp, PSRR, thermo budget in a design. Few I would posit, except the HPs and Tektronix and Marconis of the test world. How many actually look at C ESR curves and SPICE simulate the power environment ? Its my personal belief a lot of stuff gets put out there stating "I have 20 bits" but nowhere to be found is nosie and actual accuracy and drift. Thats because when you try to do a full 12 bit, 1/2 LSB over all error and temp and V, you suddenly discover how difficult that actually is. Take a look at the ploymer caps, they are an order of magnitude better ESR vs F for bulk needs. And C behaves a lot better with V. Regards, Dana. |
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