完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
嗨,
我的项目合成确定,但在奇怪的错误实现中断: 地点:1012 - 已发现时钟IOB / DCM组件对未放置在最佳时钟IOB / DCM站点对。 时钟组件放置在现场。 如果将时钟IO / DCM站点放置/锁定在同一象限中,则可以将其配对。 IO组件位于站点。 这将不允许使用IO和时钟缓冲区之间的快速路径。 如果此子设计可接受此子优化条件,则可以使用.ucf文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为警告并允许您的设计继续。 但是,强烈建议不要使用此覆盖,因为它可能导致非常差的时序结果。 建议在设计中纠正此错误情况。 下面列出了此时钟放置规则中使用的所有COMP.PIN的列表。 这些示例可以直接在.ucf文件中使用,以覆盖此时钟规则。 地点:1012 - 已发现时钟IOB / DCM组件对未放置在最佳时钟IOB / DCM站点对。 时钟组件放置在现场。 如果将时钟IO / DCM站点放置/锁定在同一象限中,则可以将其配对。 IO组件位于站点。 这将不允许使用IO和时钟缓冲区之间的快速路径。 如果此子设计可接受此子优化条件,则可以使用.ucf文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为警告并允许您的设计继续。 但是,强烈建议不要使用此覆盖,因为它可能导致非常差的时序结果。 建议在设计中纠正此错误情况。 下面列出了此时钟放置规则中使用的所有COMP.PIN的列表。 这些示例可以直接在.ucf文件中使用,以覆盖此时钟规则。 我需要两个独立的时钟,我在项目中有两个DCM。 似乎实施工具没有最佳地定位DCM。 它建议AFAIK手动限制DCM,我不知道如何做到这一点。 有人有什么想法吗? 我使用了推荐的解决方法 - 核心工作,但它不稳定。 同样有趣的是,这个错误并不总是发生。 如果我改变一些信号连接,它可能神奇地消失,然后随机重新出现。 谢谢, Blaz 以上来自于谷歌翻译 以下为原文 Hi, my projects synthesizes ok, but breaks on implementation on strange error: Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component can be paired if they are placed/locked in the same quadrant. The IO component This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "RTDL_CLK_i" CLOCK_DEDICATED_ROUTE = FALSE; > < PIN "RTDL_DecoderCLK/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; > Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component be paired if they are placed/locked in the same quadrant. The IO component will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "EL_CLK_i" CLOCK_DEDICATED_ROUTE = FALSE; > < PIN "EL_DecoderCLK/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; > I need two separate clocks and I have two DCMs in the project. It seems that implementation tools doesn't position DCM optimally. AFAIK it recommends to manualy constraint DCMs, which i don't know how to do it. Anybody has any idea? I used recommended workaround - core works, but it isn't stable. Also interesting is the fact that this error doesn't occur always. If I change some signal connections it could magically disappear, and later on randomly reappear. Thanks, Blaz |
|
相关推荐
5个回答
|
|
限制DCM的最简单方法可能是使用布局规划器。
但是,如果你 知道你想要他们的位置(即在没有给你这个错误的良好运行之后,看看在哪里 他们结束了)你可以添加行到ucf文件,如: COMP“RTDL_DecoderCLK / DCM_SP_inst”LOC = DCM_X1Y0; 使用布局规划器可以查看输入引脚附近的可用站点。 假设 已经分配了引脚,当您将DCM拖到平面布置视图中时,您将看到 连接到时钟引脚,而且很容易选择附近的DCM网站。 我唯一的原因 通常远离平面布置者,它将其输出写回我整齐的手 - 编辑过的ucf文件,几乎破坏了ucf文件的可读性。 HTH, 的Gabor - Gabor 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Probably the easiest way to constrain your DCM's is to use the floorplanner. However if you know where you want them (i.e. after a good run that doesn't give you this error, look where they ended up) you can just add lines to the ucf file like: COMP "RTDL_DecoderCLK/DCM_SP_inst" LOC = DCM_X1Y0; Using the floorplanner allows you to see the available sites near the input pins. Assuming the pins have already been assigned, when you drag the DCM into the floorplan view you will see the connection to the clock pin and than it's easy to pick a nearby DCM site. The only reason I generally stay away from the floorplanner is that it writes its output back to my neatly hand- edited ucf file and pretty much destroys the readability of the ucf file from that point on. HTH, Gabor -- GaborView solution in original post |
|
|
|
限制DCM的最简单方法可能是使用布局规划器。
但是,如果你 知道你想要他们的位置(即在没有给你这个错误的良好运行之后,看看在哪里 他们结束了)你可以添加行到ucf文件,如: COMP“RTDL_DecoderCLK / DCM_SP_inst”LOC = DCM_X1Y0; 使用布局规划器可以查看输入引脚附近的可用站点。 假设 已经分配了引脚,当您将DCM拖到平面布置视图中时,您将看到 连接到时钟引脚,而且很容易选择附近的DCM网站。 我唯一的原因 通常远离平面布置者,它将其输出写回我整齐的手 - 编辑过的ucf文件,几乎破坏了ucf文件的可读性。 HTH, 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 Probably the easiest way to constrain your DCM's is to use the floorplanner. However if you know where you want them (i.e. after a good run that doesn't give you this error, look where they ended up) you can just add lines to the ucf file like: COMP "RTDL_DecoderCLK/DCM_SP_inst" LOC = DCM_X1Y0; Using the floorplanner allows you to see the available sites near the input pins. Assuming the pins have already been assigned, when you drag the DCM into the floorplan view you will see the connection to the clock pin and than it's easy to pick a nearby DCM site. The only reason I generally stay away from the floorplanner is that it writes its output back to my neatly hand- edited ucf file and pretty much destroys the readability of the ucf file from that point on. HTH, Gabor -- Gabor |
|
|
|
谢谢你,Gabor,floorplanner确实是个好主意。
但是在UCF中编写COMP约束时,我得到了以下错误: ConstraintSystem - 在文件中:tmreciver.ucf(81):无法解析约束关联类型“COMP”。 “COMP”不是“UCF”约束格式中关联的有效约束类型。 似乎它不承认COMP? 以上来自于谷歌翻译 以下为原文 Thank you, Gabor, floorplanner is indeed good idea. But at writing COMP constraint in UCF, I got following error: ConstraintSystem - In file: tmreciver.ucf(81): Unable to resolve constraint association type "COMP". "COMP" is not a valid constraint type for association in the "UCF" constraint format. Seems that it doesn't recognize COMP? |
|
|
|
哎呀。
我一定戴着格子帽...... INST是.ucf文件的正确关键字。 问候, 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 Oops. I must have had my Lattice hat on... INST is the correct keyword for the .ucf file. Regards, Gabor -- Gabor |
|
|
|
那很有效!
但仅仅限制DCM没有成功,我不得不将I / O引脚更改为更靠近DCM的引脚。 Gabor,非常感谢! Blaz 以上来自于谷歌翻译 以下为原文 That worked! But solely constraining DCM didn't work out, I had to change I/O pins to those closer to DCM. Gabor, thanks a lot! Blaz |
|
|
|
只有小组成员才能发言,加入小组>>
2323 浏览 7 评论
2736 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2221 浏览 9 评论
3300 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2371 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
663浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
468浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
236浏览 1评论
674浏览 0评论
1870浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-10-5 04:56 , Processed in 1.248740 second(s), Total 84, Slave 68 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号