Spartan 3E安装在定制PCB板上,所有IO引脚的时钟受到大噪声的影响

当你说你的解耦遵循指南，但你没有地平面，那怎么做
你的旁路帽接地？
我希望时钟信号很容易产生问题
如果内部Vcc的旁路有一个接地路径，其中包括Vcco的接地返回路径。
接地平面的点是降低地面返回路径中的电感，这将有所帮助
避免你所看到的那种问题。
如果在Vccint引脚和a之间放置一个帽子
例如，Vcco的包装地面返回，你可以很容易地看到你的噪音
除非你有一个地平面来分流地面返回电流。
你没有
提到包，但我假设只有2个路由层，它必须是一个四边形
包。
这些已经具有显着的引线框架电感。
使用路由电源
跟踪而不是平面增加了这种电感，为您提供信号的最坏情况 
完整性。
-  Gabor
在原帖中查看解决方案



以下为原文

When you say your decoupling follows the guidelines, but you don't have a ground plane, then how do
your bypass caps tie to ground?  I would expect that the clock signal could easily create problems
if the bypass for the internal Vcc has a ground path that includes the ground return path for Vcco.
 
The point of a ground plane is to reduce the inductance in the ground return paths that would help
to avoid just the sort of issue you are seeing.  If you place a cap between the Vccint pin and a
package ground return for Vcco, for example, you could easily see the sort of noise you are
experiencing unless you have a ground plane to shunt the ground return current.  You didn't
mention the package, but I'm assuming with only 2 routing layers that it must be a quad flat
package.  These already have significant lead frame inductance.  Routing the power using
traces rather than a plane adds to this inductance giving you a worst case scenario for signal
integrity.
-- GaborView solution in original post

当你说你的解耦遵循指南，但你没有地平面，那怎么做
你的旁路帽接地？
我希望时钟信号很容易产生问题
如果内部Vcc的旁路有一个接地路径，其中包括Vcco的接地返回路径。
接地平面的点是降低地面返回路径中的电感，这将有所帮助
避免你所看到的那种问题。
如果在Vccint引脚和a之间放置一个帽子
例如，Vcco的包装地面返回，你可以很容易地看到你的噪音
除非你有一个地平面来分流地面返回电流。
你没有
提到包，但我假设只有2个路由层，它必须是一个四边形
包。
这些已经具有显着的引线框架电感。
使用路由电源
跟踪而不是平面增加了这种电感，为您提供信号的最坏情况 
完整性。
-  Gabor



以下为原文

When you say your decoupling follows the guidelines, but you don't have a ground plane, then how do
your bypass caps tie to ground?  I would expect that the clock signal could easily create problems
if the bypass for the internal Vcc has a ground path that includes the ground return path for Vcco.
 
The point of a ground plane is to reduce the inductance in the ground return paths that would help
to avoid just the sort of issue you are seeing.  If you place a cap between the Vccint pin and a
package ground return for Vcco, for example, you could easily see the sort of noise you are
experiencing unless you have a ground plane to shunt the ground return current.  You didn't
mention the package, but I'm assuming with only 2 routing layers that it must be a quad flat
package.  These already have significant lead frame inductance.  Routing the power using
traces rather than a plane adds to this inductance giving you a worst case scenario for signal
integrity.
-- Gabor

这个论坛太棒了。
感谢您的快速输入。
我使用的是四方扁平封装，我使用走线来布线接地。
如果我有一整个地面飞机会更好，我现在可以看到。
你的解释让我意识到我所看到的。
vcco和地线都有噪音，证实了你说的话。
当我用信号发生器以较慢的频率（2 MHz）替换25 MHz时钟时，我能够正常工作。
我现在正在研究振荡器电路是否可以改进，或者噪声是否只是高频和pcb的结果。
再次感谢！



以下为原文

This forum is awesome.  Thanks for your quick input.
 
I am using a quad flat package, and I use traces to route the grounding.  It would have been better had I had an entire ground plane, I can see that now.  Your explanation helped me realize what I was seeing.  Both vcco and ground lines had the noise as well, which confirmed the things you said.
 
I was able to make things work properly when I replaced the 25 MHz clock with a slower frequency (2 MHz) from a signal generator.  I'm now working on figuring out if the oscillator circuitry can be improved, or if the noise is just a consesequency of the high frequency and the pcb.
 
Thanks again!