配置后Spartan 3输入保持低电平

对不起，第一篇文章不接受附件。
配置Xilinx后输入信号保持在低电平的电路。
作为测试，我制作了一个简单的设计，包括：输入pad-> buffer  - >输出pad。
输入信号在配置之前存在，但在配置之后保持低电平。
无论Xilinx是通过JTAG还是通过XCF01S配置PROM进行编程，都会发生这种情况。
定义的I / O标准是默认值，LVTTL和LVCMOS33。
该银行的Vcco为3.3V。
GCLK7（bank0）上的输入信号不受影响，但所有其他bank 0和bank 1引脚上的输入信号都会受到影响，包括GCLK6（bank 0），GCLK5（bank 1）和GCLK4（bank 1）的信号。
PCB原理图附件。
任何和所有的帮助表示赞赏。
Spartan3 Schematic.pdf 42 KB



以下为原文

Sorry, 1st post did not accept the attachment.

Circuit where input signals get held at a low level after Xilinx is configured.  As a test, I produced a simple design consisting of: input pad-> buffer -> output pad.  Input signals are present before configuration but are held low after configuration.  This happens whether the Xilinx is progammed via JTAG or via XCF01S configuration PROM.  I/O standards defined have been default, LVTTL, and LVCMOS33.  Vcco for the bank is 3.3V.  Input signal on GCLK7 (bank0) is not affected but input signals on all other bank 0 and bank 1 pins are affected including signal of GCLK6 (bank 0), GCLK5 (bank 1) and GCLK4 (bank 1).  PCB schematic attached.

Any and all help is appreciated.
            Spartan3 Schematic.pdf ‏42 KB