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我需要实现一个简单的系统,每3ms读取一个~3kB的数据包并将其保存到SD卡。
在data_ready脉冲上创建GPIO中断并将3k数据包移动到乒乓缓冲区并且当~128kB缓冲区满时启动传输到SD存储器似乎相当紧张。 3ms中断和大SD传输都可以单独工作。 但是当我试图同时使用它们时,问题就开始出现了。 启用嵌套中断有点帮助 - 至少程序不会冻结异常,但在SD传输正在进行时,3ms GPIO中断完全被忽略。 所以,问题是:是否可以在不冲突其他中断的情况下访问SD卡? 看起来“ff.h”中的函数在后台使用DMA中断。 我想我最好在一些轮询模式下设置SD传输。 有人可以帮忙吗? 谢谢! 以上来自于谷歌翻译 以下为原文 I need to implement a simple system which reads a ~3kB packet every 3ms and saves it to SD card. It seemed quite strait forward to create a GPIO interrupt on data_ready pulse and move the 3k packet to a ping-pong buffer and when a ~128kB buffer is full initiate transfer to SD memory. Both 3ms interrupts and big SD transfers worked fine separately. But when I tried to use them simultaneously the problems started to show up. Enabling nested interrupts helps a little - at least the program does not freeze on an exception, but while SD transfer is in progress the 3ms GPIO interrupts are totally ignored. So, the question is: is it possible to access SD card without conflicting other interrupts? It looks like the functions from "ff.h" are using DMA interrupts in background. I guess it would be the best for me to set the SD transfers in some polled mode. Can anybody help? Thanks! |
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4个回答
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硬件布局是:
- PS SDIO通过MIO引脚(Zedboard) - 来自UARTLite和Axi-GPIO的两个PL中断 GPIO inerrupt是周期性的,并且每隔3ms由外部数据就绪脉冲激励。 UART中断是随机的(外部命令)。 在每个GPIO中断时,3kB数据被附加到乒乓缓冲器,当缓冲器满时,数据应该被发送到SDIO。 到这个时候代码很大,我真的不知道哪个部分可能有用。 UART和GPIO的ISR工作正常,UART的ISR优先级为64,GPIO的默认值为160.两个ISR都在Xil_EnableNestedInterrupts()/ Xil_DisableNestedInterrupts()之间调用,因此GPIO IS永远不会被UART ISR上的新字符混淆。 代码的SD部分使用“ff.h”中的函数,因此序列为: f_mount() - > f_mkfs() - f_open()初始化,然后在乒乓缓冲区满后再执行f_write()。 SD文件正常,但SD传输正在进行时到达的数据会丢失,因为在传输完成之前不会调用GPIO ISR。 到目前为止,我的计划是: - 使用GPIO ISR优先级 - 如果它没有帮助尝试使用XSDPs函数并将所有内容写入单个怪物文件 - 我也看到有人提到Xilinx的FreeRTOS有一个替代的SD接入实现,也许我会尝试一下 以上来自于谷歌翻译 以下为原文 The hardware is layout is: - PS SDIO via MIO pins (Zedboard) - Two PL interrupts from a UARTLite and Axi-GPIO The GPIO inerrupt is periodic and excited by and external data ready pulse every 3ms. The UART interrupt is random (an external command). On every GPIO interrupt 3kB of data are appended to a ping-pong buffer and when the buffer is full the data is supposed to be sent to SDIO. By this time the code is quite big and I don't really know which part may be useful to share. The ISRs for UART and GPIO work fine, UART's ISR priority is 64, GPIO's is default 160. Both ISRs are called between Xil_EnableNestedInterrupts() / Xil_DisableNestedInterrupts(), so that GPIO IS is never confused by a new character on UART ISR. The SD part of the code is using functions from "ff.h", so the sequence is : f_mount() -> f_mkfs() -f_open() to initialize and then f_write() after the ping-pong buffer is full. The SD files are OK, except for the data arriving while SD transfers are in progress are lost because the GPIO ISR is not called until transfer is finished. So far, my plan is to: - play with GPIO ISR priorities - if it does not help try to use XSDPs functions and write everything to a single monster file - I've also seen someone mentioning that FreeRTOS for Xilinx has an alternative SD access implementation, maybe I'll try it too |
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128kB缓冲区是PS还是PL?
我认为如果你可以在PL中处理UART和128KB缓冲区并且只有PS中断缓冲区半满/满,它会更好。 以上来自于谷歌翻译 以下为原文 Is the 128kB buffer is the PS or PL? I think it would work better if you could handle the UART and 128KB buffer in the PL and just have interrupts to the PS for buffer half full/full. |
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感谢您的建议。
我能够通过不使用PS DMA控制器和减少其他中断优先级来解决问题。 我不能同意这些问题来自A9架构,恕我直言,它更可能是由Xilinx实现ARM架构或驱动程序库(BSP)的方式引起的。 我在OMAP中使用了类似的配置,从未观察过类似的情况。 以上来自于谷歌翻译 以下为原文 Thanks for the advice. I was able to somewhat fix the problems by not using PS DMA controller and reducing other interrupt priorities. I cannot agree that these issues come from A9 architecture, IMHO it's more likely to be caused by the way Xilinx implemented ARM architecture or driver libraries (BSP). I used a similar configuration with OMAP and never observed anything like this. |
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