怎么从设备FIFO GPIF具有快速数据传输功能

我犯了一个错误。拖缆正在工作！当我提高频率（方波）在SLWR为390k（每传输128；包xfers队列16），我能得到的吞吐量（700kb／s）和接收的数据是成功的。据估计，测量吞吐量是可靠的。
现在我需要做的是与Slave FIFO异步提高传输速度。我在传输庞大的数据从FPGA到GPIF的唯一兴趣然后PC优化的Slave FIFO异步例子任何建议将不胜感激。谢谢你，乐华晨



     以下为原文
  I made a mistake. The Streamer is working! When I increase the frequency (square wave) at the SLWR to 390K (Packets per Xfer 128; Xfers to Queue 16), I can get the Throughput (700KB/s) and the received data are Successes. According to estimation, the measured throughput is reliable.
            
        Now what I need to do is increasing the transfer speed with the Slave FIFO Asynchronous. I am only interest in transferring huge data from the FPGA to GPIF and then to PC. Any suggestions to optimize the Slave FIFO Asynchronous example will be appreciated.   
            
        Thank you,   
        Lehua Chen   

嗨，乐华晨，
很高兴知道这一点。
使用“突发”可以增加吞吐量。我不确定您是否尝试了SDK附带的UBBulkSuthCink Link示例。你可以在那个项目中寻找“CyfxfxEppBurthl长度”。还有一个Read .txt来解释执行性能优化所需的步骤。
当做，
西克里希纳。



     以下为原文
  Hi Lehua Chen,
    Good to know that.
    Using "burst" you can increase the throughput. I am not sure whether you tried the USBBulkSourceSink example that comes with the SDK. You can look for "CY_FX_EP_BURST_LENGTH" in that project. Also there is a readme.txt to explain the steps needed to do performance optimizations.
    Regards,
    sai krishna.

你好，sai Krishna，
谢谢你的回复。我现在解决了这个问题。我还尝试了从FIFO同步的例子。当PCLK连接到40MHz方波（受函数发生器限制）时，我得到最大吞吐量115700 kb/s。总之，我所犯的错误如下：（1）在从FIFO异步示例中，我将SLWR连接到常数0。所以写入过程无法启动。在我把SLWR连接到函数生成器之后，写入过程就开始了。但是SLWR上的频率仅为3kHz，对于拖缆检查吞吐量是两个小。因此，我一直认为拖缆没有正确的工作方式。（2）在从FIFO同步的例子中，SLDR可以连接到常数0（可能是由于PCLK）。在我在BulkSuthink中做的优化之后，一切都很好。谢谢你的帮助，陈冠希



     以下为原文
  Hello, sai Krishna,
        Thank you for your reply.   
            
        I solved the problem now. I also tried Slave FIFO Synchronous example. When the PCLK is connected to 40MHz square wave (limited by the function generator), I get the maximal throughput 115700KB/s. I think this is reasonable.   
            
        In conclusion, the mistakes made by me are as following:   
            
        (1) In the Slave FIFO Asynchronous example, I connected the SLWR to constant 0. So the write process can not start. After I connected the SLWR to the function generator, the write process is on. But the frequency on SLWR is only 3KHz, it is two small for the Streamer to check the throughput. Therefore, I always thought the Streamer did not work in the right way.   
            
        (2) In the Slave FIFO Synchronous example, SLDR can be connected to constant 0 (maybe due to the PCLK). After optimizing as what I did in Bulksourcesink, everything is fine.   
            
        Thank you for your kind help, Sai Krishna   
        Lehua Chen   

我很乐意帮助你。
感谢您在论坛上发表您的学习，让其他客户从您的帖子中获益。
当做，
西克里希纳。



     以下为原文
  It’s my pleasure to help you.
    Thanks for posting your learnings in the forum so that the other customers will get benefit out of your posts.
    Regards,
    sai krishna.