怎么从时间戳恢复时钟频率

我在XAPP589中使用PICXO PLL设计作为通用PLL（没有收发器的版本）。
我不推荐它，因为它是加密的，无法模拟。
这留下了其他三种可能性。
1.编写一些代码以实现使用MMCM移相器输入作为调频振荡器的第二（或更高）阶DPLL。
我使用累加器在累加器上溢/下溢条件下产生正负相移。
这允许MMCM跟踪外部时钟。
在您的情况下，接收的时间戳用于生成后期/早期条件，用于模拟DPLL的相位比较器。
2.千兆位收发器（7系列和更新系列）具有TX相位调制能力，相位步长比MMCM移相器略小。
如果您有备用，它可以用作具有1000 ppm拉伸范围的VCO，就像在XAPP589中一样。
3.编写一个全数字DSP电路，用于过滤时间戳更新，并直接调制本地时钟（本地时间戳计数器）的更新。
这可能是最好的解决方案，因为您可以在估算，过滤和最终累积中使用尽可能多的精度。
一对DSP48可用于以相当高的时钟速率实现96位累加器。
有足够的精度，您的局部漂移基本上是您的从板振荡器的短期稳定性。
不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。
在原帖中查看解决方案



以下为原文

I've used the PICXO PLL design in XAPP589 as a general purpose PLL (the version without a transceiver).    I would not recommend it, because it's encrypted and can't be simulated.   This leaves 3 other possibilities.    
 
1.   Write some code to implement a 2nd (or higher) order DPLL that uses the MMCM phase shifter input as a frequency modulated oscillator.    I did this using an accumulator to generate positive and negative phase shifts on an accumulator overflow/underflow condition.     This allowed the MMCM to track an external clock.    In your case,  the received time stamp is used to generate a late/early condition that is used to emulate the phase comparator of the DPLL.  
 
2.   The gigabit tranceivers  (series 7 and newer) have TX phase modulation capability, with somewhat smaller phase steps than the MMCM phase shifters.    If you have a spare, it can be used as a VCO with 1000 ppm pull range, just like in XAPP589.
 
3.   Write an all digital DSP circuit that filters the timestamp updates, and directly modulate the updates of your local clock (local timestamp counter).  This is probably the best solution, since you can use as many bits of precision as you need in your estimates, filtering, and finally accumulation.     A pair of DSP48's can be used to implement a 96 bit accumulator at quite a high clock rate.     With enough bits of precision, your local drift will be essentially the short term stability of your slave board oscillator.
 
  
Don't forget to close a thread when possible by accepting a post as a solution.View solution in original post

我在XAPP589中使用PICXO PLL设计作为通用PLL（没有收发器的版本）。
我不推荐它，因为它是加密的，无法模拟。
这留下了其他三种可能性。
1.编写一些代码以实现使用MMCM移相器输入作为调频振荡器的第二（或更高）阶DPLL。
我使用累加器在累加器上溢/下溢条件下产生正负相移。
这允许MMCM跟踪外部时钟。
在您的情况下，接收的时间戳用于生成后期/早期条件，用于模拟DPLL的相位比较器。
2.千兆位收发器（7系列和更新系列）具有TX相位调制能力，相位步长比MMCM移相器略小。
如果您有备用，它可以用作具有1000 ppm拉伸范围的VCO，就像在XAPP589中一样。
3.编写一个全数字DSP电路，用于过滤时间戳更新，并直接调制本地时钟（本地时间戳计数器）的更新。
这可能是最好的解决方案，因为您可以在估算，过滤和最终累积中使用尽可能多的精度。
一对DSP48可用于以相当高的时钟速率实现96位累加器。
有足够的精度，您的局部漂移基本上是您的从板振荡器的短期稳定性。
不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。



以下为原文

I've used the PICXO PLL design in XAPP589 as a general purpose PLL (the version without a transceiver).    I would not recommend it, because it's encrypted and can't be simulated.   This leaves 3 other possibilities.    
 
1.   Write some code to implement a 2nd (or higher) order DPLL that uses the MMCM phase shifter input as a frequency modulated oscillator.    I did this using an accumulator to generate positive and negative phase shifts on an accumulator overflow/underflow condition.     This allowed the MMCM to track an external clock.    In your case,  the received time stamp is used to generate a late/early condition that is used to emulate the phase comparator of the DPLL.  
 
2.   The gigabit tranceivers  (series 7 and newer) have TX phase modulation capability, with somewhat smaller phase steps than the MMCM phase shifters.    If you have a spare, it can be used as a VCO with 1000 ppm pull range, just like in XAPP589.
 
3.   Write an all digital DSP circuit that filters the timestamp updates, and directly modulate the updates of your local clock (local timestamp counter).  This is probably the best solution, since you can use as many bits of precision as you need in your estimates, filtering, and finally accumulation.     A pair of DSP48's can be used to implement a 96 bit accumulator at quite a high clock rate.     With enough bits of precision, your local drift will be essentially the short term stability of your slave board oscillator.
 
  
Don't forget to close a thread when possible by accepting a post as a solution.

你好@ jmcclusk
谢谢。
你能详细说明第三点吗？
Time_stamp_comparison_out  - > filter  - > DCO（基于dsp的累加器） - > output_clock
因为output_clock是从逻辑生成的，所以我担心时间问题。



以下为原文

Hi @jmcclusk
Thank you. Can you elaborate point three in more details? 
 
Time_stamp_comparison_out -> filter -> DCO(dsp based accumulator) -> output_clock
 
I am worried about timing since output_clock is generated from logic.

你需要更准确地定义“本地时钟”。
这是5 MHz（或其他频率）的物理时钟信号吗？
或者“本地时钟”只是一个时间戳的计数器？
或者它是由本地振荡器产生的时钟使能信号，其中使能信号频率锁定到远程主设备？
如果您需要以锁定到远程主站的某个频率合成本地时钟信号，那么MMCM方法就是您的选择。
如果它是时间戳计数器，则所有数字dsp都是路径。
频率锁定的使能信号也都是数字的。
不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。



以下为原文

you need to be more precise in your definition of "local clock".     Is this a physical clock signal at 5 MHz (or some other frequency) ?      Or is the "local clock"  just a counter that is a timestamp?    Or is it a clock enable signal generated by a local oscillator, where the enable signal is frequency locked to the remote master?
 
If you need to synthesize a local clock signal at some frequency locked to the remote master,  then the MMCM approach is the way to go.    If it's a timestamp counter,  then all digital dsp is the path.      An enable signal that's frequency locked is all digital too.
Don't forget to close a thread when possible by accepting a post as a solution.