怎么将8位计数器值传送到VDAC

嘿，Meenz，你使用的是基于UDB的计数器，还是使用组件创建工具建立了自定义计数器组件？



     以下为原文
  Hey Meenz, are you using UDB based Counter or built a Custom Counter component using component creation tool?

Hi-DASG
我已经在UDB中实现了计数器。这是一个简单的实验，通过DMA对UDB的访问进行实验。
IAM附加归档的项目。你能否告诉我，我是否需要做什么特别的工作？
当做
梅茨
UDB2DAC.BangLe01.Zip
959.1 K



     以下为原文
  Hi dasg
    I have implemented the counter in UDB. It was a simple experiment to experiment the access of UDB via DMA
    I am attaching the archived project . Could you please tell me if I have to make any specific DMA setiings
     
    Regards
    meenz

•   UDB2DAC.Bundle01.zip 959.1 K  
  
  

此外，我附上工程定时器产生的请求。
当做
梅茨
UDB2DAC.BangLe02.Zip
959.1 K



     以下为原文
  Also, I am attaching the project with Timer generating the request.
     
    Regards
    meenz

•   UDB2DAC.Bundle02.zip 959.1 K  
  
  

当使用相同的时钟触发DMA和计数器（在这种情况下，定时器）时，DMA和计数器按输入时钟确定的速率工作。因此，每个增量计数从计数器有效地转移的DMA。DMA只占用一个总线时钟周期。
然而，当DMA在CPU中被触发时，您可能会连续触发它，并且每个传输在一个总线时钟周期结束。计数器按计时器确定的速率递增。因此，从状态寄存器转移到DAC的值将是不规则的。在每一个CPU触发之后，可能需要等到计数器被初始化，然后进入下一步。我希望这有帮助！



     以下为原文
  

    

• When you trigger the DMA and the counter using same clock(in this case, a Timer), DMA and the counter operates at the rate determined by input clock. Hence every incremental count from the counter is effectively transferred by DMA. DMA takes only one BUS CLOCK cycle.    
  

     
   

    

• However, when the DMA is trigger in CPU, you might be triggering it continuously and each transfer finishes in one BUS Clock period. The counter increments at the rate determined by the Timer. Hence the values transferred from the status register to DAC will be irregular. After every CPU trigger it might be necessary to wait until the counter has incermented and then move on to the next step.   
  

    I hope this helps !

嗨，u2，
谢谢你的快速反应。但是我有一个疑问。当运行DMACH CPU模式时，计数器在总线时钟上连续递增。DMA和计数器都不存在定时器依赖关系。在这种情况下，我期望每一个总线时钟，我的计数器值递增，DMA将这个值传递给DAC。但是，除了直流电平以外，我在DAC上没有得到任何输出。
当做
梅茨



     以下为原文
  Hi U2,
    Thanks for the quick response. However I have one doubt. When running DMA in CPU mode, The counter is incremented continuously at bus clock. The Timer dependency does not exist for both DMA and the counter. In such a scenario I expect that every BUS clock, my counter value is incremented and the DMA transfers this value to the DAC. However, I am not getting any output at the DAC other than a DC level.
     
    Regards
    Meenz

几个观测值
VDAC配置：VDACL速度设置为慢，因此稳定时间越长，您可能需要将其更改为快速，以改善输出处的稳定时间。项目中的输出范围设置为0～4V。在这种情况下，VDAC组件的最大更新为250kSPS。这将是对输出更新速率的限制。所以即使你的DMA能够在总线时钟传输数据（24 MHz）DAC不可更新。减少输出范围0-1V得到一个1msps产出率（4X 0-4v范围）。DMA配置：
在你的项目，如果你打算执行CPU触发，感兴趣的参数是在API的request_per_burst参数，dma_dmainitialize()。如果这个参数设置为1，则需提供每一个CPU请求转移。因此，在你的项目sincecydmachsetrequest（通道，cpu_req）是只有一次，只有先转移会发生。如果parameterrequest_per_burst设置为零，然后DMA传输的字节数指定的TD（对你来说是1）。因此，你将得到一个DC值，如你所见。DMA数据传输需要6个周期，如果therequest_per_burstparameter设置为1。无论是CPU或外部触发给DRQ终端需要6个周期，DMA取地址从TD和完成转移。然而，如果这个参数设置为零，只有第一个字节的传输需要6个周期。每隔一次换乘需要1个周期。我希望这些事情能让你走下去。



     以下为原文
  Couple of observations
   

    

• VDAC Configuration: The VDAC_Speed is set to Slow, hence settling time is higher, you might want to change it to fast to improve settling time at the output.     
  
• Output Range in your project is set to 0-4V. In this case the maximum updaterate of VDAC component is 250Ksps. This will be the limit on the output update rate. So even if your DMA is capable of transferring the data at Bus Clock(24 Mhz) DAC is not capable of updating. Reduce the output range to 0-1V to get a output rate of 1MSPS(4X of 0-4V range ).   
  

    DMA Configuration:
   

    

• In your project if you intend to perform CPU trigger, the parameter of interest is the REQUEST_PER_BURST parameter in the API, DMA_DmaInitialize(). If this parameter is set to 1, it is required to provide a CPU request for every transfer. Hence in your project since CyDmaChSetRequest(channel, CPU_REQ) is called only once, only first transfer would occur. If the parameter REQUEST_PER_BURST is set to zero then the DMA will transfer number of bytes as specified by TD(In your case it is 1). Hence you would get a DC value as seen by you.    
  
• DMA takes 6 cycles for transferring data if the REQUEST_PER_BURST parameter is set to 1. Be it CPU or External trigger given to DRQ terminal it requires 6 cycles for the DMA to fetch address from TD and complete the transfer. However if this parameter is set to zero, only the first byte transfer will take 6 cycles. Every other transfer will take 1 cycle.   
  

    I hope these things should get you going. 

嗨，u2，
非常感谢你的回复。在我的项目中，我要求连续执行1字节的TD。所以RealestyPi霹雳被设置为“0”，正如你所提到的。除此之外，我还要再做一次改变。我在CydMatdStaseCuffic（）中设置TDyAutoReXixNeXT。通过这个设置，我能够得到预期的输出。
非常感谢你的帮助。
当做
梅茨



     以下为原文
  Hi U2,
    Thanksa lot for  your response. In my project I required that the td of length 1 byte be executed continuously. So the REQUEST_PER_BURST was set to '0' as mentioned by you.  In addition to that  I made one more change. I set the TD_AUTO_EXEC_NEXT in CyDmaTdSetConfiguration(). With this setting I was able to get the expected output.
    Thanks a lot for your help
    Regards
    meenz

你好，
作为前一个实验的补充，我不想输出到VDAC，而是想通过UART读取计数器值。基本上，流程将是反-GT；DMA-GT；Buffer After DMAtransfer是完整的，通过UART读取缓冲区数据。
所发生的是，在读回数据中，计数值以4/5的步长增加，而不是不断增加。每个DMAP操作需要5个周期来进行突发读取吗？根据我以前的文章的理解，在初始延迟之后，当ReestStPiPySurb设置为“0”时，我应该期望每个周期都有一个新的数据。下面是DMASITETION。
UIT8缓冲区〔4096〕；
/ / /突发计数为1；初始CPU请求后，执行所有其他爆发不断；
#如果（定义（__c51__））通道= dma_dmainitialize（1, 0, 0、0）；#别的渠道= dma_dmainitialize（1, 0，hi16（status_reg_sts_reg__status_reg），hi16（缓冲区））；# endif //////分配TD，TD = {（1）cydmatdallocate()；如果（TD！= DMAIVALIDIDIETD）；} //执行TD和STOP。增量唯一的目的地地址cydmatdsetconfiguration（TD，n=4095，dma_invalid_td，（td_inc_dst_adr））；cydmatdsetaddress（TD，lo16（（uint32）status_reg_sts_reg__status_reg），lo16（（uint32）缓冲））；CyDmaChSetInitialTd（通道，TD）；CyDmaChPriority（通道，0）；CyDmaChEnable（通道1）；
//启动DMA CyDMACHSETIVE请求（通道，CPU-Req）；
当做
梅茨



     以下为原文
  Hi,
    As an add on to the previous experiment, instead of output to VDAC, I want to read back the counter value through UART. So basically the flow would be Counter->DMA->Buffer After DMA transfer is complete,read buffer data through UART.
    What is happening is that in the read back data, the count value increases in steps of 4/5 instead of continuously increasing. Does each DMA operation take 5 cycles for burst read? As per my understanding from previous posts, after the initial latency, I should expect a new data every cycle when the REQUEST_PER_BURST is set to '0'. following are the DMA settings.
    uint8 buffer[4096];
     /// Burst count is 1 ; After the initial CPU request, execute all other bursts continuously;
      #if (defined(__C51__))             
          channel = DMA_DmaInitialize(1, 0, 0, 0);
    #else
      channel = DMA_DmaInitialize(1, 0, HI16(Status_Reg_sts_reg__STATUS_REG), HI16(buffer) );
     #endif 
////// Allocate TD
    while(1){       
            td=CyDmaTdAllocate();
        if(td!=DMA_INVALID_TD)
          break;
          } 
/// Execute TD and stop. Increment only destination addr     
       CyDmaTdSetConfiguration(td, 4095, DMA_INVALID_TD,(TD_INC_DST_ADR) );

       CyDmaTdSetAddress(td, LO16((uint32)Status_Reg_sts_reg__STATUS_REG), LO16((uint32)buffer) );      
       CyDmaChSetInitialTd(channel, td);                    
       CyDmaChPriority(channel,0);
       CyDmaChEnable(channel, 1);
    /// Start DMA
       CyDmaChSetRequest(channel, CPU_REQ);
     
    Regards
    meenz

嗨，Meenz，
在项目中，由于突发计数设置为1，DMA链在一次传输之后终止。因此，整个TD配置需要在一次传输和每次传输之后重新加载。这会消耗一些时间。将突发计数最大化为127（最大允许），以避免这种延迟。



     以下为原文
  Hi Meenz,
    In your project since the burst count is set to 1, the DMA chain terminates after one transfer. As a result the entire TD configuration needs to be reloaded after one transfer and everytime. This will eat up some time. Increase the Burst count to maximum of say 127(maximum allowed) to avoid this delay.

你好，我需要紧急帮助在UDB实现udb或记录的实施提前谢谢你。再见



     以下为原文
  hi,
I need urgent help to implement a UDB or a documented example of implementation in UDB
thank you in advance.
bye

嗨，Meenz
我需要紧急帮助来实现UDB或在UDB最佳问候中实现的文档化示例。再见
BunjouLaMa'Jai-Beoin Daide倾注了评论IMPUE Munter UN UDB块可重构德赛普拉斯AVEC UNPSOC5 MelCI Avavices。补偿作用
EBK



     以下为原文
  Hi Meenz
    I need urgent help to implement a UDB or a documented example of implementation in UDB
best regards.
bye

    Bonjour l'ami

J'ai besoin d'aide pour comprendre comment implémenter un UDB block reconfigurable de CYpress avec un PSOC5

Merci d'avance.

Cordialement
    EBK

U2或其他：
将每个突发请求设置为0的意义是什么？这是否使DMA连续工作？如果数字大于1，你是否需要执行一个以上的请求才能得到DMA的响应？谢谢。



     以下为原文
  U2 or others:
    What is the significance of setting Request per burst to 0? Does this make the DMA operate continuously? What if the number were greater than 1, would you have to perform more than one request to get the DMA to respond? Thanks.

你好，
每个字节的请求应该总是0或1。
如果每个突发的请求被设置为0，那么在第一个突发之后的所有后续突发将被自动请求并执行。
如果每个突发的请求是1，那么在第一个突发之后的所有后续突发也必须单独请求。
关于使用0和1以外的值的问题，这是不明智的。在API实现中，“请求脉冲”值用0x01加左移位7次。因此，该值将被发送到MSB，它将决定每个突发请求是否启用。
因此，如果使用偶数（具有LSB＝0），那么它相当于每个突发请求0。如果使用奇数（带LSB＝1），则相当于每个突发请求1。
希望这有帮助。



     以下为原文
  Hi porcine_aviator,
     
    The Request Per Byte should always be either a 0 or 1.
    If the Request per Burst is set to 0, then all the subsequest bursts after the first burst will be automatically requested and carried out.
     
    If the Request per Burst is 1, then all the subsequent bursts after the first burst must also be individually requested.
     
    Regarding your question about using a value other than 0 and 1, it is not advisable to do it. In the API implementation, the "RequestPerBurst" value is ANDed with 0x01 and left shifted 7 times. Hence, the value will be sent to MSB which will determine whether Request per Burst is enabled or not.
    Hence, if you use an even number (with LSB = 0), then it is equivalent to giving Request per Burst as 0. If you use an odd number (with LSB = 1), then it is equivalent to giving Request Per Burst as 1.
     
    Hope this helps.