Nexys-Video板上的DMA音频演示项目失败

你好
这里有一个用于在Digilent Nexys板（Artix-7）上设置音频编解码器的演示项目。
运行.tcl进行项目创建后，存在以下几个问题：
1-该项目与Vivado 2017.4不兼容。
几次尝试后我解决了很多问题。
2- MicroBlaze模块设计中有6个I2C端口用于与编解码器通信，而应该有2个端口;
即SDA＆amp;
SCL。
实现设计时，BitGen因6个I2C引脚没有引脚位置而失败。
为什么存在这样的错误，我该如何处理？
注意：我设计了一个IO_BUF，它连接3个引脚并进行inout连接。
一个用于SDA，一个用于SCL。
3-在使用上述解决方法生成位文件后（不确定它是否可行），VIVADO不会生成硬件切换。
我必须使用xilinx论坛中的自定义tcl命令生成它。
4  - 强制导出到SDK后，SDK无法编程FPGA，并说没有“download.bit”文件。
Ther确实存在一个位文件，即“design_1.bit”，但SDK并没有通过结合design_1.bit和应用程序来构建“download.bit”！
请帮助解决问题。
谢谢



以下为原文

Hi
There is a demo project for setting up Audio Codec on the Digilent Nexys Board (Artix-7) here. After running the .tcl for project creation there are several problems:
1- The project is not compatible with Vivado 2017.4. I solved its many issues after several tries.
2- There are 6 I2C ports in the MicroBlaze block design for talking to the codec, whereas there should be 2 ports; i.e. SDA & SCL.
          When implementing design, BitGen fails for having no pin location for 6 I2C pins.
          Why such an error exist and how should I handle it?
          Note: I have designed an IO_BUF which connects 3 pins and makes an inout connection. One for SDA and one for SCL.
3- After bit file generation with mentioned workaround (Not sure it will work), hardware handoff is not generated by VIVADO.
          I have to generate it using custom tcl commands found in the xilinx forum here.
4- After forcing export to SDK, the SDK fails to program the FPGA, and says that there is no "download.bit" file.
          Ther does exist a bit file, namely "design_1.bit", but the SDK does not build "download.bit" by combining design_1.bit and application program!
Please help on resolving issues.
Thanks