完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
我正在使用AXI流FIFO将数据流式传输到Rx端,最终也将通过AXI总线从处理器读回。
当我尝试读取“base_address + 0x1C”时,系统挂起......以前有人遇到过这种情况吗? 在阅读“base_address + 0x1C”之前我需要采取的任何步骤 以上来自于谷歌翻译 以下为原文 I am using the AXI stream FIFO to stream data into the Rx side and eventually will be read back from the processor through AXI bus as well. When I try to read "base_address + 0x1C" , system hang... Anyone have encounter this before? Any steps that I need to take before reading "base_address + 0x1C" |
|
相关推荐
6个回答
|
|
>>我可以读取AXI Stream FIFO范围之外的其他寄存器,没有任何问题,这不是我的意思。
你能读取axi流fifo范围内的任何寄存器,还是读取所有axi流fifo访问块? 如果是的话,我会检查axi stream fifo的重置机制。 还要确保pl正在运行的是其他寄存器读取哪些工作在PL中。 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 >> I can read other registers outside the AXI Stream FIFO range without any problem That's not what I meant. Can you read any registers in the axi stream fifo range, or do all axi stream fifo access block? If yes, I'd check if reset mechanism of axi stream fifo. Also make sure pl is functioning is the other register reads which work are in PL.- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented.View solution in original post |
|
|
|
你能分享一下块设计快照吗?
AXI流FIFO如何与处理器连接? 这是基于Microblaze的设计还是基于Zynq?在您的情况下RX是什么? -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题,请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 Can you please share the block design snapshot? How is the AXI stream FIFO interfaced with processor? Is this a Microblaze based design or Zynq based? What is the RX in your case?----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
|
|
|
你能读取任何其他偏移量或正在读取挂起系统的任何偏移量吗?
- 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 can you read any other offset or is reading any offset hanging the system?- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
|
|
|
谢谢你回答这个问题。
你能读取任何其他偏移量或正在读取挂起系统的任何偏移量吗? 是的,我可以读取AXI Stream FIFO范围之外的其他寄存器而没有任何问题。 每当我读取端口0x1C或0x20时,我实例化到设计的AXI流FIFO IP就会挂断。 以上来自于谷歌翻译 以下为原文 Thanks for reply to the issue. can you read any other offset or is reading any offset hanging the system? Yes, I can read other registers outside the AXI Stream FIFO range without any problem. The AXI Stream FIFO IP that I instantiated to the design hang up whenever I read port 0x1C or 0x20. |
|
|
|
>>我可以读取AXI Stream FIFO范围之外的其他寄存器,没有任何问题,这不是我的意思。
你能读取axi流fifo范围内的任何寄存器,还是读取所有axi流fifo访问块? 如果是的话,我会检查axi stream fifo的重置机制。 还要确保pl正在运行的是其他寄存器读取哪些工作在PL中。 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 >> I can read other registers outside the AXI Stream FIFO range without any problem That's not what I meant. Can you read any registers in the axi stream fifo range, or do all axi stream fifo access block? If yes, I'd check if reset mechanism of axi stream fifo. Also make sure pl is functioning is the other register reads which work are in PL.- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
|
|
|
|
|
|
|
只有小组成员才能发言,加入小组>>
2413 浏览 7 评论
2820 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2292 浏览 9 评论
3371 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2456 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1028浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
576浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
434浏览 1评论
1998浏览 0评论
721浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-18 12:53 , Processed in 1.231327 second(s), Total 56, Slave 50 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号