真正的异步Fifo，NO CLOCK，它们是否存在于fpga世界中？

总的来说，我建议不要采用这种方法。
毫无疑问，Xilinx提供的现有FIFO IP不会容忍这种情况 - 至少在异步模式下如此。
异步FIFO在内部使用“正常”时钟交叉技术将信息从读取域带到写入域（反之亦然），以生成full / empty / almost_full / almost_empty ...信号。
这些时钟交叉器要求时钟在这些时钟交叉事件期间运行，并且可能需要几个时钟周期才能完成。
您提议的机制（使用push和pop作为“时钟”）将没有可用于使这些时钟交叉工作的时钟脉冲。
接下来的问题是“理论上可以设计这样的FIFO”。
从理论上讲，它可能是，虽然会有很多与之相关的挑战。
问题是这个结果将是一个纯粹的异步设计 - 你需要使用控制信号来驱动时钟引脚和异步预设以及清除触发器。
FPGA（及其工具）实际上并不是为处理这样​​的事情而设计的。
您将遇到的许多问题包括FPGA希望使用预先路由的时钟网络来访问时钟资源。
这些保证了可预测的时钟偏差。
由于控制信号驱动这些时钟引脚，您将不得不牺牲这些控制信号的全局网络，每个控制信号将为相对较少的触发器提供时钟，或者使用本地路由时钟 - 两者都非常低效。
此外，这些类型的电路通常具有异步竞争条件。
这些要求由事件引起的某些信号“在”由同一事件引起的其他信号之前到达。
使用Vivado使用的布局布线算法是不可能的（或者至少是非常困难的） - 它们不是为优化这些东西而构建的。
接下来，限制这件事将是一场噩梦。
XDC非常强大，并且继承的功能远远超出了预期在FPGA中使用的“正常同步”行为。
但是，在大多数情况下，这些能力不是主流，更糟糕的是，几乎从未使用过。
很少使用的东西更有可能是错误的...但即使它们确实正常工作，这将是非常困难的。
因此，尽管将这些信号（和数据）同步到现有的时钟域同样令人痛苦，但实际上可以肯定的是，这将是一种不那么痛苦的方法（并且更有可能工作......）
）
Avrum



以下为原文

In general, I would recommend against pursuing this approach.
 
It is certainly fair to say that the existing FIFO IP provided by Xilinx will not tolerate this - at least in asynchronous mode. The asynchronous FIFOs internally use "normal" clock crossing techniques to bring information from the read domain to the write domain (and vice versa) for the generation of the full/empty/almost_full/almost_empty... signals. These clock crossers require the clock to be running during these clock crossing events and may take several clock periods in order to do them. The mechanism that you are proposing (using the push and pop as "clocks") will not have clock pulses available to make these clock crossings work.
 
The next question is "Is it theoretically possible to design a FIFO like this". Theoretically, it probably is, although there will be lots of challenges associated with it. The problem is that this result will be a pure asynchronous design - you will need to use control signals driving clock pins and asynchronous presets and clears of flip-flops. FPGAs (and their tools) really aren't designed to handle things like this.
 
Among many of the problems you will face is the fact that FPGAs expect the pre-routed clock networks to be used to access clocked resources. These guarantee predictable skew of the clock. With control signals driving these clock pins, you will either have to sacrifice global networks for these control signals which will each clock relatively few flip-flops, or else use locally routed clocks - both are very inefficient.
 
Furthermore, these kinds of circuits often have asynchronous race conditions. These require that certain signals caused by an event arrive "before" other signals caused by the same event. This is impossible (or at least extremely difficult)  to guarantee with the place and route algorithms used by Vivado - they are just not built to optimize these things.
 
Next, constraining this thing will be a nightmare. XDC is very powerful, and inherits abilities far beyond "normal synchronous" behavior expected to be used in FPGAs. But, for the most part, these abilities are not mainstream or, even worse, are almost never used. Things that are rarely used will be more likely to be buggy... But even if they do work properly, this is going to be very difficult.
 
So, as painful as it may be to synchronize these signals (and the data) to an existing clock domain, in the end, it is virtually certain that this will be the less painful approach (and the one more likely to work...)
 
Avrum

谢谢Avrumw
我不同意，因为一般来说这不是编码的方式，
但
对于这个接口，数据是FAST爆发，然后没有， 
没有时间重新同步时钟或启用第二个时钟，
所以，如上所述，真正的异步fifo对于这个应用来说非常棒，
至于设计它的挑战， 
是的我同意，这就是为什么我要问的是有人知道的IP /设计，
如果没有，它到设计阶段，
没那么难， 
异步逻辑，使用锁存器进行速度设计，或者从三级逻辑转换为两级逻辑，现在很难，
到目前为止，我唯一的“同步”想法是采用IOB SERDES的时钟频率约为1 GHz对数据和频闪进行采样， 
然后是一些逻辑来决定时钟的位置，并在推送到较慢/较宽的时钟域之前获取数据。
但
与以前的可能性相比，这是一个简单的异步fifo。



以下为原文

thank you Avrumw
 
I do not dis agree in that in general this is not the way to code,
 
BUT 
 
for this interface, data comes in a FAST burst, then nothing ,
     no time to re syncronise clock or enables to a second clock,
 
So  yes a real asynchronous fifo as described would be great for this application, 
  
As for the challenge of designing it,
   Yes I agree, thats why I'm asking is there an IP / design around that anyone knows of,
 
if not, its over to the design phase, 
 
Not that difficult,
   asynchronous logic , designs using latches for speed,  or converting from three level to two level logic, now thats hard,
  
The only 'synchronous' idea I have so far is to sample the data and strobe with IOB SERDES's clocking at around 1 GHz, 
    then some logic to decide where the clock was, and grab the data , before pushing to a slower / wider clock domain.
 
BUT
 
thats horrendous compared to what used to be possible, a simple asynchronous fifo.
 
 
 
 
 

你说快，但有多快？
你可以使用输入时钟的两个边缘吗？
还有时钟如何停止？
例如，如果您使用上升时钟沿采样输入数据，但时钟变为低电平并停止为低电平，则在突发结束时您将有一个额外的时钟沿将数据从捕获寄存器移至内部（LUT）
或块）RAM。
如果没有，则需要将数据直接从I / O引脚运行到RAM并满足RAM的设置时间。
如果其中任何一个为真（额外的时钟沿或能够满足从引脚写入RAM的设置时间），那么设计FIFO可能并不太难。
您的读时钟将是自由运行的，因此唯一困难的部分是为RAM的写地址构建同步格雷码计数器。
这是必要的，以避免额外的时钟采取二进制计数，重新编码为灰色，然后在下一个写时钟捕获它。
这有多难取决于FIFO所需的深度。
你还说有一个快速爆发然后“没什么”。
是否有最低保证时间“没有？”
如果是这样，也可以用来简化FIFO，特别是如果你不太关心延迟。
例如，您可以检测输入时钟停止并对写入地址进行采样，然后读出该地址。
这必然意味着FIFO需要至少与最大突发大小一样深。
-  Gabor



以下为原文

You say FAST, but how fast?  Could you possibly use both edges of the input clock?  And also how does the clock stop?  If for example you use the rising clock edge to sample input data, but the clock then goes low and stops low, you'd have one extra clock edge at the end of the burst to move data from the capture register to an internal (LUT or block) RAM.  If not, you'd need to run data directly from the I/O pin to the RAM and meet the RAM's setup time.  If either of these is true (extra clock edge or ability to meet setup time to write RAM from the pin), then it may not be too hard to design a FIFO.  Your read clock would be free-running, so the only hard part is building a synchronous Gray code counter for the write address to the RAM.  This is necessary to avoid the extra clock to take a binary count, re-code it to Gray, and then capture it on the next write clock.  How hard this is would depend on the required depth of the FIFO.
 
Also you say there is a fast burst and then "nothing."  Is there a minimum guaranteed time of "nothing?"  If so that could also be used to simplify the FIFO, especially if you're not too concerned about latency.  You could for example detect the input clock stopping and sample the write address, then read out up to that address.  This would necessarily mean that the FIFO needs to be at least as deep as the maximum burst size.
-- Gabor

谢谢gszaks
我不想详细说明，因为我问的是一个具体问题，而不是在一般性讨论之后， 
但我可以看到你来自哪里。
对于任何其他人，
数据没有时钟。
系统有数据进入启用脉冲，
数据有效5 ns，数据中心的上升沿脉冲，
一阵数据，每5ns一个新样本，最多128个，然后一秒钟没什么
至于FPGA fifo是否足够快，我不知道，这就是为什么我问的是有没有真正的异步FIFO。
这是一个有趣的问题，
谢谢你的想法，



以下为原文

Thanks gszaks 
 
I did not want to go into detail, as I'm asking a specific question, not after a general discussion,
    but I can see where your coming from.
 
 
For any one else,
 
there is no clock with the data. 
 
the system has data coming in with an enable pulse,
data is valid 5 ns, a rising edge pulse in the centre of the data,
 
a burst of data , one new sample every 5ns , a maximum of 128, then nothing for a second
 
 
As to if a FPGA fifo could be fast enough, I don't know, thats why I was asking about are there any real asynchronous fifos around.
 
its an interesting problem,
 
thanks for the ideas,
 
 
 
 
 
 
 

@drjohnsmith
>>现在fpga中的所有十五都需要连续时钟
我不认为这是真的。
只要您符合时序要求，就没有理由不能停止FPGA中任何模块的时钟，包括存储器等。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

@drjohnsmith
>> All the fifos in the fpga now days need continuous clocks
 
I don't think this is true. As long as you comply with the timing requirements, there is no reason the clocks to any block in an FPGA can't be stopped, including memories etc.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

你当然可以停止时钟，但问题是当你停止写时钟时，即使你的读时钟连续运行，最后的数据也不会从FIFO中出来，直到写时钟再次启动（可能在1秒后
这个案例）。
我以为你可以从BUFGMUX驱动时钟，所以当你刚刚进入数据（FIFO不为空）时，你要等到爆发完成（可能是一个超时计数器），然后
将写时钟短暂切换到读时钟或其他连续时钟，并提供足够的额外写时钟以完成冲洗FIFO。
-  Gabor



以下为原文

You can certainly stop the clock, but the problem is that when you stop the write clock, even if your read clock runs continuously, the last data will not come out of the FIFO until the write clock starts up again (possibly 1 second later in this case).On thought I had was that you could drive the clock from a BUFGMUX, so that when you've just had data coming in (FIFO goes not empty), you wait until the burst is finished (possibly a time-out counter) and then briefly switch the write clock over to the read clock or some other continuous clock and provide enough additional write clocks to finish flushing out the FIFO.-- Gabor

正如gszakacs所说， 
一个需要时钟进入fifo以使标志工作， 
停止时钟，旗帜停止。
把自己的时钟注入差距的有趣想法， 
会有想法，



以下为原文

As gszakacs says, 
    
one needs the clock into the fifo for the flags to work,
      stop the clock , an the flags stop.
 
interesting idea to inject our own clock in the gap,
    will have a think,
 

我倾向于认为您需要尽快将传入数据同步到内部（自由运行）时钟。
即
比FIFO早得多。
您可能需要在输入端使用一些异步技术。
但是然后将正常的同步技术作为你的fifo（或其他逻辑）的输入。
我不认为数据速率是200MHz可能的麻烦（但太高太容易应用过采样技术）。
根本问题是设计这样一个同步器，输入端有非自由运行的“时钟”。
我知道我在某个地方（可能在这些论坛上）读到有类似问题的其他人。
“非自由运行的时钟”在我脑海中作为搜索时间，但我的Google-Fu目前还没有出现任何问题。
它可能值得一个答案记录或类似的东西 - 也许不是真正常见的需要，但肯定不是太遥远。
祝你好运。
- 标记



以下为原文

I tend to think you'd need to synchronize the incoming data to an internal (free running) clock as soon as possible.  I.e. much sooner than a FIFO.  You'd need to probably use some asynchronous techniques right at the inputs.  But then normal synchronous techniques as input to your fifo (or other logic).  I don't think data rate is the trouble 200MHz is possible (But is too high too easily apply oversampling techniques).
 
The root trouble is designing such a synchronizer with the non-free running "clock" on the input. I know I read somewhere (on these forums maybe) about someone else with similar problems.  "Non-free running clock" sticks in my head as the search time, but my Google-Fu isn't turning up anything at the moment.
 
It probably deserves an answer record or something similar - maybe not really common need, but certainly not too far fetched.
 
Good luck.
 
--Mark
 

谢谢markcurry
麻烦的是，真正的异步FIFO已经存在于FPGA世界中。
好吧，我怀疑旧款是否足够快，但它们已经消失了， 
所以我们必须忍受我们拥有的同步逻辑。



以下为原文

thank you markcurry
 
The hassle is that true asynchronous fifos used to exist in FPGA world.
 
OK, I doubt if the old ones would be fast enough, but they have gone ,
     so one has to live with the synchronous logic we have.