[问答]

基于FPGA的电机控制中的信号同步

问答对人有帮助，内容完整，我也想知道答案 0 您可能知道，对于电机控制，三个相电流和位置在一个瞬间首先使用ADC进行采样。采样信号首先用于Park变换以获得I_d / I_q，并进行电流调节以产生电压命令Ud / Uq。 Ud / Uq与位置信号一起用于逆Park变换。由于FPGA的性质，Ud / Uq计算需要几个周期才能用于逆Park变换。但是，逆Park变换可以直接使用该位置，因为此信号没有处理。但是必须使用与相位电流相对应的Ud / Uq，该相电流与位置信号相同。我知道我可以在位置信号上手动添加一些延迟，以弥补位置和Ud / Uq信号之间的时间差。但是，我不认为这可能是一般方式。我想知道是否有一些通用的方法来同步信号。目前使用FPGA进行电机控制或其他应用的做法是什么。 BTY，我正在使用Kintex和Simulink以及System Generator for DSP。提前感谢您的帮助。以上来自于谷歌翻译以下为原文 As you may know, for motor control, three phase currents and position first sampled with ADC at one time instant. The sampled signals are first used to in Park Transform to get the I_d/I_q, and do the current regulation to generate voltage commands Ud/Uq. The Ud/Uq together with the position signal are used in the inverse Park Transform. Due to the FPGA nature, it takes several cycles for the Ud/Uq calculation before they can be used for inverse Park Transform. However, the inverse Park Transform can use the position directly as there is no processing on this signal. But it is necessary to use the Ud/Uq corresponding to the phase currents which are sampled at the same as the position signal. I know I can add some delays manually on the position signal to make up the time difference among the position and Ud/Uq signals. However, I don't think this could be a general way. I am wondering whether there are some general ways to synchronize the signals. What are the current practices in using FPGA for motor control or other applications. BTY, I am using Kintex with Simulink and System Generator for DSP. Thank you in advance for your kind help. 0
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答案对人有帮助，有参考价值 0 @fbaiwhether你必须纠正这个延迟取决于你的控制循环的带宽与延迟。对于循环来说，“通知”可能太低了。如果你真的想平衡延迟，这就是我在这样的情况下做的事情：设计一个通用延迟线，它根据类型和延迟进行参数化。然后在数据路径中，记录参数中计算模型的延迟。最后用数据路径的累积延迟声明延迟信号的延迟。如果您使数据路径中的延迟数保持最新，则未延迟的信号延迟将自动与其匹配。 - 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。以上来自于谷歌翻译以下为原文 @fbai whether you have to correct this delay depends on the bandwidth of your control loop vs the latency. It's probably way too low for the loop to "notice". If you actually want to balance the delays, here is what I do in situations like this: design a generic delay line which is parameterized based on type and delay. Then in your datapath, record the latencies of you calculation models in parameters. Finally declare a delay for the undelayed signal with the cumulative delay of the datapath. If you keep your latency numbers in the datapath up to date, the undelayed signal delay will automatically match it. - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented.

2019-4-22 12:44:12 评论举报陈苏文

答案对人有帮助，有参考价值 0 @muzaffer非常感谢您的回复。实际上，这就是我已经做过的事情。它适用于一些简单的模型。但是，如果模型变得更大且更复杂，手动声明延迟将导致很多开销。这就是我寻找一种更简单，更通用的方法来解决问题的原因，特别是当开关频率非常高时。我在这里附加了控制回路的一部分。这里，DAC，Park变换，PI和逆向停车变换被视为单独的模块。有没有什么方法可以确保每个模块的输入同步？以上来自于谷歌翻译以下为原文 @muzaffer Thank you very much for your response. Actually, this is what I have already done. It works well for some simple models. However, if the model gets larger and more complicated, manually declaring a delay will lead to much overhead. That is the reason I am looking for a simpler and more general method to solve the problem, especially when the switching frequency goes very high. I am attaching part of the control loop here. Here DAC, Park Transform, PI and Inverse Park Transform are viewed as individual modules. Are there any methods that can make sure the inputs of each module are synchronize?

2019-4-22 12:51:58 评论举报刘丽