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嗨,我使用数据表中的示例代码来使用DMA读取4个ADC通道。代码看起来很好,我正在寻找我正在寻找的样本。问题是,它们处于错误的缓冲区。我把电压设置在引脚2-5上,这应该对应于ADC通道AN2-5。但是当我在引脚2(AN2)上加上电压时,在通道4上得到样本。与销3同上,它在通道5上出现噘嘴。接下来的两个别针什么也不做。下面是我的设置代码:我正在调试调试模式中的DMA缓冲区。这仅仅是我不理解某事的一个例子吗?例如,我假设AD1CSL中的位对应于ANX信道一一对应。所以当我说“0x00 3C”时,它会扫描通道2-5,谢谢!
以上来自于百度翻译 以下为原文 Hi, I used the example code out of the datasheet to read 4 ADC channels using DMA. The code seems to work fine and I am getting the samples I am looking for. The problem is they are in the wrong buffers. I am putting voltage on pins 2-5 which is supposed to correspond to ADC channels AN2-5. But when I put a voltage on pin 2 (AN2) I get samples on channel 4. Ditto with pin 3; it comes pout on channel 5. The next two pins do nothing. Here is my set up code: AD1CON1bits.FORM = 0; // Data Output Format: Integer AD1CON1bits.SSRC = 2; // Sample Clock Source: GP Timer starts conversion AD1CON1bits.ASAM = 1; // ADC Sample Control: Sampling begins immediately after conversion AD1CON1bits.AD12B = 1; // 12-bit ADC operation AD1CON1bits.SIMSAM = 0; // Samples multiple channels individually in sequence AD1CON2bits.BUFM = 0; AD1CON2bits.CSCNA = 1; // Scan Input Selections for CH0+ during Sample A bit AD1CON2bits.CHPS = 0; // Converts CH0 AD1CON3bits.ADRC = 0; // ADC Clock is derived from Systems Clock AD1CON3bits.ADCS = 63; // ADC Conversion Clock //AD1CHS0: A/D Input Select Register AD1CHS0bits.CH0SA = 0; // MUXA +ve input selection (AIN0) for CH0 AD1CHS0bits.CH0NA = 0; // MUXA -ve input selection (Vref-) for CH0 //AD1CHS123: A/D Input Select Register AD1CHS123bits.CH123SA = 0; // MUXA +ve input selection (AIN0) for CH1 AD1CHS123bits.CH123NA = 0; // MUXA -ve input selection (Vref-) for CH1 //AD1CSSH/AD1CSSL: A/D Input Scan Selection Register //AD1CSSH = 0x0000; AD1CSSL = 0x003C; // Scan AIN2, AIN3, AIN4, AIN5 inputs AD1CON1bits.ADDMABM = 0; // DMA buffers are built in scatter/gather mode AD1CON2bits.SMPI = 3; // 4 ADC buffers AD1CON4bits.DMABL = 3; // Each buffer contains 8 words IFS0bits.AD1IF = 0; // Clear the A/D interrupt flag bit IEC0bits.AD1IE = 0; // Do Not Enable A/D interrupt AD1CON1bits.ADON = 1; // Turn on the A/D converter I am looking at the DMA buffers in debug mode. Is this simply a case me not understanding something? For example I assume the bits in AD1CSSL correspond to the ANx channels one-to-one. So when I say "0x003C" it scans channels 2-5. Thanks! |
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调试器SEZ BufferA为0x47 A0,BufferB为0x47 40。这里是DMA缓冲区定义:从数据表复制。这里是DMA init代码:空隙inITDMA0(空隙){DMA0CONBITS。AMODE=2;//配置DMA用于外围间接模式DMA0CONBITS.MODE=2;//配置DMA用于连续乒乓模式DMA0PAD=0x0300;//点DMA到ADC1BUF0 DMA0CNT=47;//32 DMA请求(4个缓冲器,每个具有8个字)DMA0Req=13;//选择ADC1作为DMA请求源DMA0STATA=Y-BuuTiTiNyDMACORM(&BufferA);DMA0STATION DMACORM(ANP;BufferB);IFS0BITS DMA0IF=0;/ /清除DMA中断标志位IEC0BIT.DMA0IE=1;/ /设置DMA中断允许位DMA0CONTITE。举例说明。我尝试添加缓冲区为AD0&1,数据表似乎表明DMA必须开始在AD0。这给出了不同但仍然混乱的结果。
以上来自于百度翻译 以下为原文 Debugger sez BufferA is 0x47A0 and BufferB is 0x4740. Here is the DMA buffer definitions: // DMA buffers #define NumAdcSamples 8 struct { unsigned int Adc1Ch0[NumAdcSamples]; unsigned int Adc1Ch1[NumAdcSamples]; unsigned int Adc1Ch2[NumAdcSamples]; unsigned int Adc1Ch3[NumAdcSamples]; unsigned int Adc1Ch4[NumAdcSamples]; unsigned int Adc1Ch5[NumAdcSamples]; } BufferA __attribute__((space(dma))); struct { unsigned int Adc1Ch0[NumAdcSamples]; unsigned int Adc1Ch1[NumAdcSamples]; unsigned int Adc1Ch2[NumAdcSamples]; unsigned int Adc1Ch3[NumAdcSamples]; unsigned int Adc1Ch4[NumAdcSamples]; unsigned int Adc1Ch5[NumAdcSamples]; } BufferB __attribute__((space(dma))); As copied from the datasheet. Here is the DMA init code: void initDma0(void) { DMA0CONbits.AMODE = 2; // Configure DMA for Peripheral indirect mode DMA0CONbits.MODE = 2; // Configure DMA for Continuous Ping-Pong mode DMA0PAD = 0x0300; // Point DMA to ADC1BUF0 DMA0CNT = 47; // 32 DMA request (4 buffers, each with 8 words) DMA0REQ = 13; // Select ADC1 as DMA Request source DMA0STA = __builtin_dmaoffset(&BufferA); DMA0STB = __builtin_dmaoffset(&BufferB); IFS0bits.DMA0IF = 0; //Clear the DMA interrupt flag bit IEC0bits.DMA0IE = 1; //Set the DMA interrupt enable bit DMA0CONbits.CHEN=1; // Enable DMA } Again from the datasheet example. I tried adding buffers for AD0&1; the datasheet seemed to indicate DMA has to start at AD0. This gave different but still scrambled results. |
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更多信息:信道顺序应该是:AD2,AD3,AD4,AD5,但看起来我得到:AD4,AD5,AD2,AD3。
以上来自于百度翻译 以下为原文 More info: The channel order should be: AD2, AD3, AD4, AD5 but it looks like i"m getting: AD4, AD5, AD2, AD3 |
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我认为缓冲器必须对齐特定的地址偏移量。(DS70182B,DMA)在分散/聚集模式下,ADC为信道号(0到31)和当前信道号(0~7)提供地址(如您所指定的)。根据我的计算,ADC可以处理的DMA的量是:32(通道)* 8(每个信道的字)* 2(每个字字节)=512字节,所以DMA缓冲器的起始地址应该对齐到512的倍数(即使你从不使用更高的信道)。
以上来自于百度翻译 以下为原文 I think the buffers must be aligned specific address offsets. (DS70182B ,DMA) In Scatter/Gather mode the ADC supplies addresses for the channel-number (0 to 31) and the current sample-number within this channel (0 to 7 , as you specified). From my calculation the amount of DMA which can be addresses by the ADC is: 32 (channels) * 8 (words per channel) * 2 (bytes per word) = 512 bytes So the starting address for the DMA buffers should be aligned to a multiple of 512 (even if you never use higher channels) |
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