时钟模式怎么在单个合成运行中覆盖所有情况

您没有向我们提供足够的信息来回答这个问题。
至少你需要告诉我们你正在使用什么工具--Vivado或ISE，因为两者之间的答案非常不同。
我假设您正在使用Vivado（因为您提到了set_case_analysis，这是一个Vivado命令）。
在Vivado中，默认情况下所有时钟都是相关的 - 所以如果你没有做任何例外，所有时钟将被认为是彼此同步并且“正常”定时 - 这将包括通过时钟多路复用器的所有时钟组合之间的路径（包括
可能没有意义的组合）。
但要真正回答这个问题，你需要告诉我们你的时钟结构 - 所有输入时钟在哪里，它们来自哪里，它们运行的​​频率，它们经过的时钟管理设备（MMCM / PLL / DCM）
，MUX是（可能是所有BUFGMUX）。
有了这些信息，我们可以回答您的问题。
Avrum



以下为原文

You haven't provided us anywhere near enough information to answer this question.
 
At the very least you need to tell us what tool you are using - Vivado or ISE, since the answer is very different between the two.
 
I am assuming you are using Vivado (since you mention set_case_analysis, which is a Vivado command). In Vivado, all clocks are related by default - so if you don't do any exceptions, all clocks will be considered synchronous to eachother and timed "normally" - this will include paths between all combinations of clocks that go through clock multiplexers (including combinations that probably don't make sense).
 
But to really answer the question, you need to show us your clock structure - where are all the input clocks, where do they come from, what frequencies do they run at, what clock management devices (MMCM/PLL/DCM) they go through, where the MUXes are (presumably all BUFGMUX).
 
With this information, we can probably answer your question.
 
Avrum

谢谢Avrum
我假设你正在使用Vivado。
我的问题很笼统，但我现在会尝试更具体地说明我的问题。
我有两个125 MHz的输入时钟..
它们彼此不同步。
它们不通过alock管理设备（MMCM / PLL / DCM）。
它们与BUFGMUX复用。
选择器可以动态地在它们之间进行切换，因此两个选项都应该由Static Timing Analaysis覆盖。
在ASIC中，我们的方法是使用时钟模式，每种模式都有不同的set_case_analysis。
这是因为我们假设如果我们不放置set_case_analysis，STA可能只处理一个时钟。
根据你的回答，我理解对于Vivado，我们应该在没有set_case_analysis约束的情况下离开多路复用器。
我对么？
谢谢
艾米尔



以下为原文

Thanks Avrum
 
I am using Vivado as you assumed.
My question was general, but I will try now to be more specific about my issue.
I have two input clocks of 125 MHz..
They are not synchronous to eachother.
They do not go through a lock management devices (MMCM/PLL/DCM).
They are muxed with BUFGMUX.
The selector can sitch between them dynamically, so both options should be covered by Static Timing Analaysis.
 
In ASIC our approach is to have clock modes, each mode with a different set_case_analysis. This is because we assume that if we do not put set_case_analysis, the STA might handle only one clock. 
From your answer I understand that for Vivado we should just leave the mux without set_case_analysis constraint. Am I correct?
 
Thanks
Amiel
 
 

查看时钟指南http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdfhttp://www.xilinx.com/training/downloads/7-series-clocking-resources.pptx
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

check clocking guide

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

http://www.xilinx.com/training/downloads/7-series-clocking-resources.pptxThanks and Regards
Balkrishan
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