如何正确获取高速数据是FPGA

我有一些源同步系统，它可以在8条线路上为FPGA提供DDR数据。
时钟频率在> 500 MHz范围内。
我知道我需要使用ISERDES和IDELAY来正确捕获这些数据。
8 ISERDES提供64位数据。
为了校准8条线，我需要在输入端给出固定的64位已知数据并调整idelay直到我得到正确的数据。
但是当我只提供64位已知数据时，一切都很好，并且在chipcope上很长时间没有出现错误。
但是当我提供实际数据时，所有ISERDES都有错误的值。
有些ISERDES的错误率很低，有些则很高。
我的问题是，由于已知的数据发送技术无法正常工作，我能做些什么来获取我的实际数据而不出错？



以下为原文

I have some source synchronous system that is giving DDR data to FPGA on 8 lines. Frequency of clock is in the range of > 500 MHz.

I know I need to use ISERDES and IDELAYs to capture this data correctly. 8 ISERDES are giving 64 bits data.

In order to calibrate 8 lines, I need to give fixed 64 bit known data at input and adjust idelay until i get correct data. BUT When I give just 64 bit known data, everything is fine and no error comes for a long time on chipscope.

But when I give actual data, all ISERDES have values in error. Some ISERDES have low error rate and some have high.

My question is, what can I do to get my actual data without error as known data sending technique is not working?