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我正在用VHDL编写FFT算法,我需要进行一些位反转。
似乎在没有编写附加功能的情况下执行此操作的唯一方法是在“循环”中执行此操作,即逐个重新分配/重新连接位,如下所示: rev_order“110” 这给了我完美的结果 - 它快速且没有复杂的逻辑。 现在来问题: 正如您所看到的,我已经反转了3位,这对于8点FFT是足够的,但是如果点数将高于8,则需要手动添加额外的“nat_order(x)”信号。我正在尝试制作 我的设计尽可能灵活,这种方法不会使它非常通用,即灵活,除非可以按GENERIC方式添加位,具体取决于点数,即如果address_width = 4,即16点.. rev_order 是否有可能以通用方式添加额外的信号? 是否有其他方法可以非常快速地实现相同的位反转结果? 亲切的问候, 巢穴 以上来自于谷歌翻译 以下为原文 I’m writing an FFT algorithm in VHDL and I need to do some bit-reversal. It seems that the only way to do it without writing an additional function, which would do it in a “looping”-way, is to re-assign/re-wire the bits one by one, like this: rev_order <= nat_order(0) & nat_order (1) & nat_order (2); -- e.g “011” => “110”This gives me the perfect result - it’s fast and no complicated logic behind it. Now to the problem: As you can see, I’ve reversed 3 bits, which is sufficient for 8 point FFT, but would require additional “nat_order(x)” signals be added manually if the number of points would be higher than 8. I am trying to make my design as flexible as possible and this method does not make it very generic, i.e. flexible, unless it’s possible to add the bits in the GENERIC fashion, depending on the number of points, i.e. if address_width = 4, i.e 16 points.. rev_order <= nat_order(0) & nat_order (1) & nat_order (2) & nat_order (3); -- nat_order (3) should be generic..Is it possible to add additional signal in generic fashion? Is there may be an other way to achieve the same result of bit-reversal very fast? Kind Regards, Den |
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6个回答
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我认为简单的“for ... generate”可能是最简单的解决方案。
就像是: BIT_REVERSE:对于i在0到WIDTH-1生成 sig_rev(ⅰ) 我相信这是完全可综合的,只要您使用的通用在更高级别定义。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 I think that a simple "for .. generate" would probably be the easiest solution. Something like: BIT_REVERSE: for i in 0 to WIDTH-1 generate sig_rev(i) <= sig_orig(WIDTH-1-i);end generate;I believe that this is fully synthesizable as long as the generic you use is defined at a higher level. View solution in original post |
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书房,
它的硬件(不是软件)。 由于您的问题,通用设计通常在工具中表现不佳。 这些工具需要在开始时知道位宽,分配,引脚等,以分配导线,LUT,DFF等。 在合成之前,必须将影响硬件数量或使用的变量解析为固定数量。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 Den, Its hardware (not software). A generic design usually does poorly through the tools due to your problem. The tools need to know the bit widths, assignments, pins, and so on at the beginning to assign wires, LUTs, DFFs and so on. A 'variable affecting the amount or use of hardware must be resolved to a fixed number before synthesis. Austin Lesea Principal Engineer Xilinx San Jose |
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Obvoiusly。
我没有在任何一点上说过我希望“硬件”在合成后变量,并且它不是什么命令“泛型”。这个论坛上的人严重过度使用的词语:“思考硬件,而不是软件”,“它是硬件” ,“硬件这和硬件”,我的问题与此无关,请不要反对 - “因为有些人不理解”。 我希望我的IP-Core用户能够在实际合成之前以通用方式设置宽度(再次 - 显然)。 这是仿制药的用途。 它与VHDL功能和我的综合工具功能有关,可以将其转换为适当的设计。 我的问题是,是否有可能做这种泛型,我可以根据通用输入改变我之前发布的代码,当然它必须在合成之前完成。简单就是这样。 答案可能是 - “它肯定会很方便,但遗憾的是不可能”或这些界限之间的某种东西。 既然你没有说,这是可能的,我会假设,这是泛型的限制,这是不可能的。 我的第二个问题仍然存在:是否可能有另一种方法可以非常快速地实现相同的位反转结果? 或者你如何进行通用位反转? 亲切的问候 巢穴 以上来自于谷歌翻译 以下为原文 Obvoiusly. I didn't say at any point that I want "hardware" to be variable after synthesis, and it's not what command "generic" does. People on this forum seriously overuse phrases like: "Think Hardware, not software", "It's hardware", "hardware this and hardware that", my question has nothing to do with that and please refrain from wirting - "Because some people don't understand". I want a user of my IP-Core to be able to set width in generic fashion, before the actual synthesis (again - obviously). It's what generics are for. It has something to do with the VHDL capabilities and my synthesis tool capabilities to translate it into proper design. And my question was if it's possible to do this kind of generics, where I can alter the code I posted previously depending on the generic input and of course it must be done before synthesis. Simple as that. The answer could be - "It surely would be convenient, but it's regretfully not possible" or something between those lines. Since you didn't say, that it's possible, I will assume, it's the limitation of generics and it's not possible. My second question still stands: Is there may be an other way to achieve the same result of bit-reversal very fast? Or how do you do generic bit reversal? Kind Regards Den |
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我认为简单的“for ... generate”可能是最简单的解决方案。
就像是: BIT_REVERSE:对于i在0到WIDTH-1生成 sig_rev(ⅰ) 我相信这是完全可综合的,只要您使用的通用在更高级别定义。 以上来自于谷歌翻译 以下为原文 I think that a simple "for .. generate" would probably be the easiest solution. Something like: BIT_REVERSE: for i in 0 to WIDTH-1 generate sig_rev(i) <= sig_orig(WIDTH-1-i);end generate;I believe that this is fully synthesizable as long as the generic you use is defined at a higher level. |
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我不理解你反对以“循环方式”进行位反转。
一个简单的程序循环(不需要生成循环)可以使用对象的大小作为循环限制来反转任何大小对象的位,如标准逻辑向量。 程序循环不会增加延迟或硬件,而是手动将其写出,就像在仅使用位选择和连接的示例代码中一样。 - Gabor 以上来自于谷歌翻译 以下为原文 I don't understand your objection to doing bit reversal in "a looping way." A simple procedural loop (generate loop is not required) can reverse the bits of any sized object like a standard logic vector using the object's size as the loop limit. A procedural loop does not add latency or hardware vs. writing it out by hand as in your example code that uses only bit selections and concatenation. -- Gabor |
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gszakacs写道:
我不理解你反对以“循环方式”进行位反转。 好吧我也不在了。 当你在多个项目上工作12个小时时会发生类似的事情。 解决方案非常简单 - 不要让事情复杂化。 一个简单的for循环使用泛型,正如你所说的或生成循环(除了你不能把它放到进程中如果你想让它由于某种原因同步)工作完全正常并具有相同的结果。 所以线程关闭了。 我将提供“acceptas Solution”towhollender的帖子,因为它也是一种做法。 以上来自于谷歌翻译 以下为原文 gszakacs wrote:Well neither am I anymore. Something like that happens when you work for 12 hours on multiple projects. The solution is very simple - do not make things complicated. A simple for loop with generics, as you said or generate loop (except that you can't put it into process If you want to make it synchronyous for some reason) works perfectly fine and have the same results. So the thread is closed. I will give "accept as Solution" to whollender's post, since it's a way of doing it too. |
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