当PSoC3处于睡眠模式时，睡眠调节器是否在操作中递送1，8V？

这是你提出来的一个有趣的话题。让我一个接一个地回答你的问题。PSoC3/PSoC5器件通常具有以下的复归器：
模拟调节器为核心，VCCA数字调节器为核心，VCCD休眠调节器RAM等，在休眠期间的I2C调节器的I2C块，而在睡眠睡眠调节器通常为睡眠领域，在主动模式操作，VCCA和VCCD的支持来自模拟和数字调节器。
在Hibernate模式下，除Hibernate调节器之外的所有调节器都关闭。这就产生了所谓的保活信号，并将其提供给需要保持状态的芯片上电路。
在睡眠模式下，操作几乎没有什么不同。在睡眠模式中，禁用每个调节器。睡眠调节器转动了。这个改革器电源VCCA和VCCD。睡眠有意思的是，这个调节器不连续供电。该调节器周期性地断续地断电。这叫“嗡嗡声”。蜂鸣器间隔被确定为寄存器值。



     以下为原文
  Its an interesting topic that you have brought up. Let me answer your question one by one. PSoC3/PSoC5 device typically has the following reggulators:
   

    

• Analog regulator for core, VCCA    
  
• Digital regulator for core, VCCD    
  
• Hibernate regulator for RAM etc during hibernate    
  
• I2C Regulator for I2C block while in sleep    
  
• Sleep reggulator for Sleep domain   
  

    Typically, in active mode operation, the VCCA and VCCD suppies come from thhe Analog and digital regulators. 
    In hibernate mode, all the regulators except hibernate regulator is turned off. This generates what is called keep alive signal and provides it to necessary on chip circuitry that is responsible for state retention.
    In Sleep mode the operation is little different. In sleep mode, every regulator is disabled. The sleep regulator is turned. This reggulator powers VCCA and VCCD. The interesting thing with sleep is, this regulator is not supplied power continuously. Thhis regulator is powered intermittently on a periodic basis. This is called ''buzzing". The buzzing interval is determined a register value. 

除此之外，嗡嗡间隔实际上间接地控制了实际的功率消耗。如果由于某种原因，VCCA和VCCD上的电容器快速放电，则可能需要增加蜂鸣器频率。
还要注意，如果使用I2C地址匹配来唤醒设备，则I2C调节器被打开。



     以下为原文
   In addition to this, the buzz interval actually controls the actual power consumtion indirectly. If for some reason the capacitor on VCCA and VCCD discharges quickly, it might be necessary to increase buzz frequency.
    Also note that if I2C address match is used to wake up the device, the I2C regulator is turned on.

谢谢你的答案U2。
我大体上理解了你所说的话。我相信问题会在我尝试的时候出现。
当做。



     以下为原文
  Thanks for your answer U2.
    I have understood in general what you've said. I supose that the problems will come later, when I try it...
    Regards.

再次问好，
在供应了2，8V电池的话题之后，我遇到了另一个疑问：
我曾想过通过2，8V电池提供VDDD和VDDA引脚。然后，假设内部模拟和数字调节器提供对应的部件1.8V，对吗？
但是Vddio呢？是否有可能提供所有的I/O引脚与内部的1，8V的调节器？或者，我必须提供所有的I/O端口与外部2，8V电池？在我的情况下，我有兴趣提供所有的I/O端口1.8V。
谢谢。当做。



     以下为原文
  Hello again,
    following the topic of the supply with the 2,8V Battery, i have encountered with another doubt:
    I've thought supply Vddd and Vdda pins through 2,8V Battery. Then, it's supposed that the internal Analog and Digital regulators supply their corresponding parts with 1.8V, right?
    But what about the Vddio? Is it possible supply all the I/O pins with the internal 1,8V of the regulators? Or do I have to supply all the I/O ports with the external 2,8V battery? In my case, I'm interested in supply all the I/O ports with 1.8V.
    Thanks. Regards.

我不是专家，但我认为如果你把VDIOS绑到VCCA和VCCD轨道上，你应该得到1.8V的所有。



     以下为原文
   I'm no expert on this,but I think if you tie the VDDIOs to the VCCA and VCCD rails,you should get 1.8V for all of them.

VDIOS是GPIOS操作所需的电源。一般来说，VDDIOs必须由单独的调节器提供。如果用VCCA短路，VCCD可以在所有引脚上得到1.8V，但是我们还没有尝试过。请注意，如果你把VCCA/VCCD连接到VDIOS并把它放在睡眠中，你可能会看到奇怪的行为。因为在睡眠模式中，VCCA和VCCD的调节器不是一直存在的。这些调节器以预定的速率被接通，以在VCCA和VCCD上充电电容器。如果使用这些CPACER提供VDDIOs，它们可能以更快的速率放电。



     以下为原文
  The VDDIOs are supplies required for the GPIOs to operate. Generally VDDIOs have to supplied from a seperate regulator. If shorted with VCCA, VCCD you might get 1.8V on all the pins, but we have not tried it yet. Note that if you tie VCCA/VCCD to VDDIOs and put the device to sleep you might see weird behavior. Because in Sleep mode, the regultors for VCCA and VCCD are not on always. These regulators are turned On at predetermined rate to charge the capacitors on VCCA and VCCD. If VDDIOs are supplied using these cpacitors, they might discharge at a faster rate. 

谢谢大家。
我明白你说的话。但是，正如你所说的，可以通过寄存器来改变睡眠调节器的嗡嗡声周期。因此，如果你设置一个短的嗡嗡声，以提供更快的电容器的VCCA和VCCD，将有可能解决冲突？
当做。



     以下为原文
  Thank's everyone.
    @U2: I understand what you say. But, as you have also said, it's possible to change the buzz periode  of the Sleep Regulator by register. Therefore, if you set up a short periode of buzzing in order to supply faster the capacitors of Vcca and Vccd, would be possible to solve the conflict?
    Regards.

TROITS，通常如果你观察到我们推荐一个特定值的电容在VCCA和VCCD端子上的PSoC3设备。这些值是基于内部调节器一致操作所需要的。如果你把VCCA/VCCD连接到VDDIO，你可能会增加额外的电容。我不会劝阻你这样做，但你总是可以给它一个镜头，看看它是否工作没有任何问题。
在连接VCCA/VCCD到VDDIO之后，你甚至可以尝试以更高的频率嗡嗡叫这个设备，但是我们过去没有做过这样的事情。



     以下为原文
  Trotis, generally if you observe we recommend a specific value of capacitor on the VCCA and VCCD terminals of PSoC3 device. These values are based on what is required for the internal regulator to operate consistently. If you connect VCCA/VCCD to VDDIO, you might end up adding additional capacitance. I would not discourage you from doing this, but you could always give it a shot to see if it works without any issues.
    You can even try Buzzing the device at a higher frequency after connecting VCCA/VCCD to VDDIO, but we have not done anything like that in the past.

谢谢U2。我试试看。
当做。



     以下为原文
  Thank's U2. I'll try it.
    Regards.

谢谢U2。我试试看。
当做。



     以下为原文
  Thank's U2. I'll try it.
    Regards.

KEPP我们通过这个线程更新，因为你正在做一些新颖的东西。



     以下为原文
  Kepp us updated via this thread, since you are doing something novel.

考虑它完成了。但暂时，我在其他问题上工作。
谢谢你的支持。



     以下为原文
  Consider it done. But for the time being, I'm working in other issues.
    Thank's for your support.