I2C通信需要被拉到3.3V应该使用什么尺寸的上拉电阻？

我不明白你是什么意思离开低在3.0V。请你谈谈对这个。
最大值和最小值的上拉电阻完全取决于总线电容。你可以在以下链接提供的I2C规格：http://www.nxp.com/documents/other/39340011.pdf - 32页的最大和最小上升时间规格。最佳值的上拉电阻也取决于你想使用标准的或快速模式。
标准模式粗略计算了6.67k最大值。你可以计算基于模式所需的精确值。
最好的问候，
普什克



     以下为原文
   I did not get what do you mean by leaving the low at 3.0V. Can you please elaborate on this. 
     
    Maximum and minimum value of pull up resistance entirely depends on the bus capacitance. You can refer to the I2C spec available at the following link: http://www.nxp.com/documents/other/39340011.pdf - page 32 for the maximum and minimum rise time specifications. Optimum value of pull up resistor will also depend on the mode you want to use - Standard or Fast mode.
     
    A rough calculation for standard mode gives a maximum value of 6.67K. You can calculate the exact value based on the mode required.
     
    Best regards,
    Pushek

我有一个示波器，当我把它连接到数据线，甚至是时钟线，并通过它发送数据，它显示逻辑高3.3V和逻辑低3.0V，我不知道还有什么可以解释它。我的理解是，逻辑低应该更接近0伏特，正如我之前从其他搜索中所说的，4.7K欧姆电阻器应该是好的。在I2CHW用户模块或其他任何地方，我没有看到任何参数，这将允许我更改逻辑零点的引用。我真的不认为这是我找到问题的地方，因为我的PWM模块工作完美（3.3高，0低）。下面是我的I2C通讯的信息，请有人在这里帮助我：
VCC：3.3伏
芯片：CY8C27
用户模型：I2CHW
模式：400千赫快速模式
最大母线电容：10pF
上拉电阻：4.7K欧姆
在任何人问之前，是的，我的O范围设置为一个合适的采样率。
K



     以下为原文
  I have an oscilloscope, when I attach it to either the data line or even the clock line and have data sent through it, it reveals logic high at 3.3V and logic low at 3.0V, I'm not sure how else to explain it.  My understanding is that logic low is supposed to be closer to 0 volts and as I've stated previously from other searching, a 4.7k ohm resistor should be fine.  I didn't see any parameters in the I2CHW user module, or anywhere else, that would allow me to change the reference of logic zero.  I don't really think that's where I'd find the problem anyway since my PWM module is working perfectly (3.3 high, 0 low).  Below is the info for my I2C comms, please someone help me here:
     
    Vcc: 3.3 volts
     
    chip: CY8C27443
    user mod: I2CHW
    mode: 400kHz fast mode
    max bus capacitance: 10pF
    pull-up resistor: 4.7k ohm
     
    And before anyone asks, yes I have my o-scope set to a proper sampling rate.
     
    K

有没有串联电阻连接在I2C线路上？此外，逻辑0何时以3.0V的形式出现？当PSoC1在总线上写入数据时，还是当主机正在写入数据时？
最好的问候，
普什克



     以下为原文
   Do you have any series resistor connected connected on the I2C lines? Also, when does the logic 0 comes as 3.0V? When PSoC1 is writing any data on the bus or when master is writing data?
     
    Best regards,
    Pushek

本文将帮助您清除上拉电阻问题的空气。
DSCIRCUITS.COM/CONTION/VIIGIN -I2C-PLU-UP电阻的影响



     以下为原文
   This article should help you clear the air on the pull-up resistors issue.
     dsscircuits.com/articles/effects-of-varying-i2c-pull-up-resistors.html

从两条I2C线中分离出每一件事物，并让程序在一个循环中运行，看看电压水平和波形是否与上述网页相似。如果这接近于正确的，那么就是外部电路引起了这个问题。如果电压仍然是错误的，请查看是否可以使用其他一组引脚再次尝试。



     以下为原文
  Disonnect every thing from the two I2C lines and let the program rrun in a loop, see if the voltage level and waveform is simliar to that above web page. If that is close to the correct one, then it is the external circuit that causing the problem. if the voltage is still wrong, see if you can use other set of pins to try again.

这也可能是由于I2C引脚的驱动模式。I2C引脚的驱动模式是什么？
对于I2C操作，通常建议将驱动模式设置为“开漏驱动低”，这意味着当写入DAT寄存器的1时，IO状态为开路漏极，并使用外部拔出来拔起，当低电平写入DAT寄存器时，IO状态被强拉低。开车到地面。
查看此链接获得更多信息，HTTP://www. CyPress？COM/？RID＝39496



     以下为原文
  This could possible also be due to drive mode of the I2C pin. What is the driver mode of the I2C pins? 
    For I2C operation it is generally recommended to have the drive mode set to "Open Drain Drive Low", which means when a 1 written to the dat register, the IO state is open drain and pulled up using external pull up, when a low is written to the dat register, the IO state is pulled low with a strong drive to ground.
    See this link for more info, http://www.cypress.com/?rID=39496