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您使用的是哪个版本的ISE？
我没有记住那些存在一段时间的逻辑。
你尝试过RTL方法吗？
A 以下为原文
Interesting,
which version of ISE you using ?
I dont rember the logicore added being around for a while .
have you tried the RTL approach
A <= B + C
Also, why 100 plus adders ? the spartan 6 runs at a few 100 MHz, so you can use one adder many times .
Ken chapman did a few great apps on how to do this sort of thing , hes the king of low level Spartan 6 work,
but generaly the tools do a greta job of fitting things in.
Have you set timing constraints ?
the tools effectivly do a try and improve aproach. If you have no constraints, and an empty FPGA , then the tools can just spread the things out , and be slow.
lots of registers is the answer to speed.
have a look through
http://www.xilinx.com/support/documentation/application_notes/xapp522-mux-design-techniques.pdf
http://forums.xilinx.com/t5/Synthesis/Fast-adders/td-p/118696
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/About-technology-mapping/td-p/116240/highlight/true
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