请问“2”在这个表达中意味着什么？

2是复制因子。
这意味着在2之后的{}之间定义的位应该被复制两次。
如果2是3则意味着将位复制三次，等等。它与写入相同：
wire [5：0] fs_delay = fs_fixed_delay  -  {frame_sync_offset [3]，frame_sync_offset [3]，frame_sync_offset};
Verilog 2001中添加了此语法。
-  Gabor
在原帖中查看解决方案



以下为原文

The 2 is a replication factor.  It means the bits defined between the {} following the 2 should be replicated twice.  If the 2 had been a 3 it would mean replicate the bits three times, etc.  It is the same as writing:
 
wire [5:0]   fs_delay = fs_fixed_delay - {frame_sync_offset[3],frame_sync_offset[3],frame_sync_offset}; 
 
This syntax was added in Verilog 2001.
-- GaborView solution in original post

2是复制因子。
这意味着在2之后的{}之间定义的位应该被复制两次。
如果2是3则意味着将位复制三次，等等。它与写入相同：
wire [5：0] fs_delay = fs_fixed_delay  -  {frame_sync_offset [3]，frame_sync_offset [3]，frame_sync_offset};
Verilog 2001中添加了此语法。
-  Gabor



以下为原文

The 2 is a replication factor.  It means the bits defined between the {} following the 2 should be replicated twice.  If the 2 had been a 3 it would mean replicate the bits three times, etc.  It is the same as writing:
 
wire [5:0]   fs_delay = fs_fixed_delay - {frame_sync_offset[3],frame_sync_offset[3],frame_sync_offset}; 
 
This syntax was added in Verilog 2001.
-- Gabor

gszakacs写道：
Verilog 2001中添加了此语法。
只是选择尼特 - 但我很确定这个功能已经在Verilog-1995中了。
（IEEE 1364）。
它已经有一段时间了。
- 标记



以下为原文

gszakacs wrote:

 
This syntax was added in Verilog 2001.

Just picking nits - but I'm pretty sure this feature was already in Verilog-1995.  (IEEE 1364).
 
It's been around a while.
 
--Mark

我有所纠正。
我不知道这叫什么，但我在转到Verilog 2001之后才遇到它。我认为它是与+：和 - ：部分选择语法一起添加的。
不过回顾1995年的LRM，我看到“复制”已经存在。
不幸的是，Verilog 2001 LRM没有更改栏（或者至少我的副本没有）所以2001年增加的内容并不明显。
顺便提一下，复制需要一组额外的大括号。
即2 {x}需要在大括号内{2 {x}}，否则会出现语法错误。
那个人往往会咬我，因为不清楚为什么需要外括号来区分复制的内容和复制品的数量。
-  Gabor



以下为原文

I stand corrected.  I didn't know what this was called, but I only came across it after moving to Verilog 2001.  I thought it was added along with the +: and -: part select syntax.  However looking back at the 1995 LRM I see "replication" was already there.  Unfortunately the Verilog 2001 LRM doesn't have change bars (or at least my copy doesn't) so it's not obvious what was added in 2001.
 
By the way note that replication requires an extra set of braces.  i.e. the 2{x} needs to be within braces as {2{x}} or you will get a syntax error.  That one tends to bite me because it's not clear why the outer braces are needed to distinguish what is being replicated and what the number of replicas are.
-- Gabor

gszakacs写道：
顺便提一下，复制需要一组额外的大括号。
即2 {x}需要在大括号内{2 {x}}，否则会出现语法错误。
那个人往往会咬我，因为不清楚为什么需要外括号来区分复制的内容和复制品的数量。
再次告诉我Verilog如何比VHDL更好;）
----------------------------是的，我这样做是为了谋生。



以下为原文

gszakacs wrote:
 
By the way note that replication requires an extra set of braces.  i.e. the 2{x} needs to be within braces as {2{x}} or you will get a syntax error.  That one tends to bite me because it's not clear why the outer braces are needed to distinguish what is being replicated and what the number of replicas are.

Tell me again how Verilog is better than VHDL ;)
----------------------------Yes, I do this for a living.

顺便提一下，复制需要一组额外的大括号。
即2 {x}需要在大括号内{2 {x}}，否则会出现语法错误。
那个人往往会咬我，因为不清楚为什么需要外括号来区分复制的内容和复制品的数量。
它不是真正的“额外”一对括号。
复制是串联运算符的一部分;
当你进行连接时，它只意味着什么。
LRM明确说明了这一点（iEEE1364-2005条款2.1.14  - “连接”）
只能应用于连接的运算符是复制，它由非负的，非x和非z常量表达式（称为复制常量）之间的连接表示，在括号中包含在一起
因此，复制只能在连接运算符内，但在连接运算符中，您可以执行任意数量的复制
分配z = {a，2 {b}，3 {c}，3 {d，e，2 {f}}};
请注意，并非每个复制都需要在一组大括号中 - 它只是复制必须位于连接运算符中。
Avrum



以下为原文

By the way note that replication requires an extra set of braces.  i.e. the 2{x} needs to be within braces as {2{x}} or you will get a syntax error.  That one tends to bite me because it's not clear why the outer braces are needed to distinguish what is being replicated and what the number of replicas are.
 
Its not really an "extra" pair of braces. Replication is a part of the concatenation operator; it only means anything when you are doing concatenation. The LRM states this clearly (iEEE1364-2005 clause 2.1.14 - "Concatenation")
 
An operator that can be applied only to concatenations is replication, which is expressed by a concatenation
preceded by a non-negative, non-x and non-z constant expression, called a replication constant, enclosed
together within brace characters
 
So, the replication can only be inside a concatenation operator, but within the concatenation operator you can do any number of replications
 
assign z = {a, 2{b}, 3{c}, 3{d,e,2{f}}};
 
Note, that its not that each replication needs to be in a set of braces - its just that the replication must be in a concatenation operator.
 
Avrum

嗯.... ISIM不同意你的看法。
//错误：HDLCompiler：806  - “C：/ Projects / junkola / junk /../ SPI / replica.v”第25行：“{”附近的语法错误.// assign z = {a，2 {b}，
3 {c}，3 {d，e，2 {f}}}; // ISIM对此感到满意：指定z = {a，{2 {b}}，{3 {c}}，{3 {d
，即，{2 {F}}}}};
LRM：
另一种形式的连接是复制操作。
第一个表达式应为非零，非X和非Z常量表达式，第二个表达式遵循连接规则。
这个例子重复“w”4次。{4 {w}} //这相当于{w，w，w，w} a [31：0] = {1'b1，{0 {1'b0}}}
;
//非法。
RHS变为{1'b1，; a [31：0] = {1'b1，{1'bz {1'b0}}};
//非法。
RHS变为{1'b1，; a [31：0] = {1'b1，{1'bx {1'b0}}};
//非法。
RHS变为{1'b1，;下一个示例说明了嵌套连接：{b，{3 {a，b}}} //这相当于{b，a，b，a，b，a，b}
请注意，所有LRM示例都具有用于复制的“额外”括号（对于无效复制因子而言，第一个示例是非法的，而不是语法）。
-  Gabor



以下为原文

Ummm....  ISIM does not agree with you.
 
// ERROR:HDLCompiler:806 - "C:/Projects/junkola/junk/../SPI/replica.v" Line 25: Syntax error near "{".
// assign z = {a, 2{b}, 3{c}, 3{d,e,2{f}}};

// ISIM is happy with this:
assign z = {a, {2{b}}, {3{c}}, {3{d,e,{2{f}}}}};
 
LRM:
 
Another form of concatenation is the replication operation. The first expression shall be a non-zero, non-X
and non-Z constant expression, the second expression follows the rules for concatenations. This example
replicates "w" 4 times.
{4{w}} // This is equivalent to {w, w, w, w}
a[31:0] = {1’b1, {0{1’b0}} }; //illegal. RHS becomes {1’b1,;
a[31:0] = {1’b1, {1’bz{1’b0}} }; //illegal. RHS becomes {1’b1,;
a[31:0] = {1’b1, {1’bx{1’b0}} }; //illegal. RHS becomes {1’b1,;

The next example illustrates nested concatenations:
{b, {3{a, b}}} // This is equivalent to {b, a, b, a, b, a, b}
 
Note all LRM examples have the "extra" braces for replications (this first examples are illegal for invalid replication factor, not syntax).
-- Gabor

我想我的立场得到了纠正！
谢谢Gabor！
Avrum



以下为原文

I guess I stand corrected!
 
Thanks Gabor!
 
Avrum

avrumw写道：
我想我的立场得到了纠正！
你们两个人是这里的顶级Verilog大师:)
那么，再次告诉我，为什么Verilog比VHDL更好！
----------------------------是的，我这样做是为了谋生。



以下为原文

avrumw wrote:
I guess I stand corrected!

You two guys are the top Verilog gurus here :)
 
So, tell me again, why Verilog is better than VHDL!
----------------------------Yes, I do this for a living.

那么，再次告诉我，为什么Verilog比VHDL更好！
真？
你真的想开始这场辩论吗？
:-)我一直把它作为一项政策，绝不参与伪宗教辩论！
我接受这两种语言都有它们的位置 - 嘿，我甚至可以（几乎没有）用VHDL进行设计。
我会把它留在“它是我学到的语言，并且使用最多，因此更舒服”。
顺便说一下，SystemVerilog是要走的路。
既然Vivado模拟器最终可以与SystemVerilog一起使用，我希望在“纯粹的”Verilog中尽可能少地做。
（对于那些想知道的人，使用Vivado Synthesis的SystemVerilog综合工作非常好，到目前为止，我还没有发现Vivado仿真中的SystemVerilog存在任何重大问题）。
Avrum



以下为原文

So, tell me again, why Verilog is better than VHDL!
 
Really? Do you really want to start this debate? :-) I have always made it a policy never to get involved in pseudo-religious debates!
 
I accept that the two languages have their place - hey, I can even (barely) design in VHDL. I will leave it at "Its the language that I learnt first and use most, and hence am more comfortable with".
 
Any by the way, SystemVerilog is the way to go. Now that the Vivado simulator can finally work with SystemVerilog, I expect to be doing as little as possible in "pure" Verilog. (And for those of you that are wondering, SystemVerilog synthesis with Vivado Synthesis works very well, and, so far, I haven't found any major problems with SystemVerilog in Vivado simulation).
 
Avrum

SystemVerilog是要走的路。
既然Vivado模拟器最终可以与SystemVerilog一起使用，我希望在“纯粹的”Verilog中尽可能少地做。
（对于那些想知道的人，使用Vivado Synthesis的SystemVerilog综合工作非常好，到目前为止，我还没有发现Vivado仿真中的SystemVerilog存在任何重大问题）。
听到，听到......
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

SystemVerilog is the way to go. Now that the Vivado simulator can finally work with SystemVerilog, I expect to be doing as little as possible in "pure" Verilog. (And for those of you that are wondering, SystemVerilog synthesis with Vivado Synthesis works very well, and, so far, I haven't found any major problems with SystemVerilog in Vivado simulation).
 
 
Hear, hear ...
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

avrumw写道：
那么，再次告诉我，为什么Verilog比VHDL更好！
真？
你真的想开始这场辩论吗？
:-)我一直把它作为一项政策，绝不参与伪宗教辩论！
这不是伪宗教。
这是实际的宗教！
----------------------------是的，我这样做是为了谋生。



以下为原文

avrumw wrote:
So, tell me again, why Verilog is better than VHDL!
 
Really? Do you really want to start this debate? :-) I have always made it a policy never to get involved in pseudo-religious debates!

This isn't pseudo-religion. This is ACTUAL religion!
----------------------------Yes, I do this for a living.

>>这不是伪宗教。
这是一个实际的宗教！我知道它有一本“书”，我可以拿出先知，但你对神灵的建议是什么？
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

>> This isn't pseudo-religion. This is ACTUAL religion!

I know that it has a "book"  and I can come up with prophets but what do you propose for a deity?- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.