如何设置输入信号的时序

嗨，set_input_delay命令指定输入端口相对于设计接口处的时钟边沿的输入路径延迟。
在考虑应用板时，此延迟表示以下之间的相位差：a。
数据从外部芯片通过电路板传播到FPGA器件的输入封装引脚，和b。
相对参考板时钟。
因此，输入延迟值可以是正数或负数，具体取决于器件接口的时钟和数据相对相位。请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug903的第50页
-vivado-使用-constraints.pdf
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,

The set_input_delay command specifies the input path delay on an input port relative
to a clock edge at the interface of the design. When considering the application board, this
delay represents the phase difference between:
a. The data propagating from an external chip through the board to an input package
pin of the FPGA device, and
b. The relative reference board clock.
Consequently, the input delay value can be positive or negative, depending on the clock
and data relative phase at the interface of the device.
Check page 50 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug903-vivado-using-constraints.pdfThanks,Vijay
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谢谢你的帮助
我正在使用xilinx ise 14.2并尝试实现仲裁器puf。
为此，我需要使上延迟路径等于低延迟路径，因此仅在物理属性上进行中继。



以下为原文

Thanks for your help 
 
I am using xilinx ise 14.2 and trying to implement arbiter puf. for this purpose i need to make upper delay path equivelant to lower delay path and hence relay on physical properties only. 
 

我不清楚你想要达到什么目标。
您是在谈论将延迟路由到FPGA（这将是电路板布局和外部布线的函数）还是延迟嵌入FPGA？
如果是后者，则可以使用OFFSET约束来约束输入接口，以对适用输入的性能设置限制。
这需要知道输入信号的定时。
但是，在同步设计中，所有输入应该由已知时钟注册，因此只要满足捕获触发器所需的建立/保持时间，实际输入延迟就不相关。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

It isn't clear to me what you want to achieve. Are you talking about routing delay TO the FPGA (which will be a function of the board layout and external routing) or delay INSIDE the FPGA?
 
If it is the latter, you can constrain the input interface using the OFFSET constraint to set limits on the performance of the applicable inputs. This requires knowledge of the timing of the incoming signals.
 
However, in synchronous design, all inputs should be registered by a known clock so the actual input delay is not relevant as long as the required setup/hold times for the capturing flip-flop are met. 
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"That which we must learn to do, we learn by doing." - Aristotle

换句话说，我有来自实例A的2个输出到实例B.我希望这些输出同时到达。
我该怎么做 ？



以下为原文

In other words, I have 2 outputs from instance A going to instance B. I want these outputs arrive on same time. How can I do it ?

这些实例是FPGA内部的实际实例，对吧？
如果信号与已知时钟同步，则A的输出在相同时间到达B时无需担心，因为重要的是信号是由相同的时钟边沿采样的。
通过为Xilinx工具提供采样时钟频率并执行静态时序分析，您可以确保满足各个捕获触发器的设置时间。
如果来自A的两个输出是异步的或将完全以组合方式处理，那么我认为在尝试使它们在同一时间到达目标逻辑时会遇到问题。
您约束所使用的资源并可能将MAXD​​ELAY约束应用于相应的网络，但我仍然认为结果不准确。
我不推荐这种方法。
也许您可以提供有关设计和数据路径的更多详细信息？
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

These instances are actual instantiations inside the FPGA, right?
 
You don't need to be concerned if the outputs from A arrive at B at the SAME time if the signals are synchronous to a known clock because what matters is that the signals are sampled by the same clock edge. You ensure that the setup times for the respective capture flops is met by providing the Xilinx tools with the sample clock frequency and performing static timing analysis.
 
If the two outputs from A are asynchronous or will be dealt with purely combinatorially then I think you will have problems trying to make them arrive at the destination logic at precisely the same time. You constrain the resources used and possibly apply a MAXDELAY constraint to the respective nets but I still think the results would be imprecise. I wouldn't recommend this approach.
 
Perhaps you could provide more detail on the design and the datapath(s) in question?
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"That which we must learn to do, we learn by doing." - Aristotle