如何使用xapp1052设计PCIe BMD示例？

嗨，
我认为您需要查看应用程序以了解如何生成有效负载。
据我所知，数据包是以应用程序GUI中指定的固定模式启动的，然后通过链接发送。
我相信您尝试理解的数据端口是用于传输和接收的trn接口。
Yuo可以在pcie核心用户指南中找到接口详细信息。对于virtex-6设备，请参阅ug517。
如果你看一下xapp1052文档“探索总线主设计”部分，它说
启动器使用特定数据模式发送Memory Writes。
每个DWORD
有效负载中包含写DMA数据模式寄存器的内容（参见“写DMA”
数据模式（WDMATLPP）（014H，R / W），“第31页）。
因此，您可能需要更改DMA模块中的逻辑以获得自己的流量模式。
问候，
KR
--------------------------------------------------
--------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用的帖子。感谢 -
------------------------- ------------------------
-------------------
在原帖中查看解决方案



以下为原文

Hi ,
 
I think you need to look into the application to understand how the payload is generated.
 
As far as i understand the packets are initiated with fixed pattern specified int he application GUI and then they are sent across the link.
I believe the data ports you are trying to understand are trn interface for transmit and receive.
Yuo can find the interface details in the pcie core userguide.Like ug517 for virtex-6 device.
 
If you look at the xapp1052 document " Exploring the Bus Master Design" section , it says
 
 
 
The initiator sends Memory Writes with a specific data pattern. Each DWORD
 
in the payload contains the contents of the Write DMA Data Pattern register (see “Write DMA
Data Pattern (WDMATLPP) (014H, R/W),” page 31).
 
So probably you need to change the logic in the DMA modules for having your own traffic pattern.
 
 
Regards,
KR
 
--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------View solution in original post

嗨，
我认为您需要查看应用程序以了解如何生成有效负载。
据我所知，数据包是以应用程序GUI中指定的固定模式启动的，然后通过链接发送。
我相信您尝试理解的数据端口是用于传输和接收的trn接口。
Yuo可以在pcie核心用户指南中找到接口详细信息。对于virtex-6设备，请参阅ug517。
如果你看一下xapp1052文档“探索总线主设计”部分，它说
启动器使用特定数据模式发送Memory Writes。
每个DWORD
有效负载中包含写DMA数据模式寄存器的内容（参见“写DMA”
数据模式（WDMATLPP）（014H，R / W），“第31页）。
因此，您可能需要更改DMA模块中的逻辑以获得自己的流量模式。
问候，
KR
--------------------------------------------------
--------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用的帖子。感谢 -
------------------------- ------------------------
-------------------



以下为原文

Hi ,
 
I think you need to look into the application to understand how the payload is generated.
 
As far as i understand the packets are initiated with fixed pattern specified int he application GUI and then they are sent across the link.
I believe the data ports you are trying to understand are trn interface for transmit and receive.
Yuo can find the interface details in the pcie core userguide.Like ug517 for virtex-6 device.
 
If you look at the xapp1052 document " Exploring the Bus Master Design" section , it says
 
 
 
The initiator sends Memory Writes with a specific data pattern. Each DWORD
 
in the payload contains the contents of the Write DMA Data Pattern register (see “Write DMA
Data Pattern (WDMATLPP) (014H, R/W),” page 31).
 
So probably you need to change the logic in the DMA modules for having your own traffic pattern.
 
 
Regards,
KR
 
--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

谢谢kotir的回复。
但我仍然不明白它是如何工作的。
你有图表或绘图来帮忙吗？
您是否认为最好从带有PIO示例的xapp1022 PCIe开始？
谢谢，
安德烈



以下为原文

Thanks kotir for your reply. 
But I still don't understand how it works. Do you have a diagram or drawing to help?
 
Do you think it is better to start with the xapp1022 PCIe with PIO example instead?
 
Thank you,
Andre