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我正在使用ISE为基于Artix-7的电路板编写一些VHDL。
在我的约束文件中,时钟定义如下: ##时钟信号NET“clk100mhz”LOC =“E3”| IOSTANDARD =“LVCMOS33”; #Bank = 35,Pin name = IO_L12P_T1_MRCC_35,Sch name = CLK100MHZNET“clk100mhz”TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 KHz HIGH 50%; 我生成了一个信号,该信号在时钟的上升沿切换,在我的逻辑分析仪上,它显示2.1kHz的频率,无论我在约束文件中更改数量。 无论我把它设置为时钟的频率,我的样本都是> 20倍。 我有什么理由读2.1kHz吗? 如果您需要更多代码/信息,请询问。 帮助将被贬低。 以上来自于谷歌翻译 以下为原文 I'm writing some VHDL for an Artix-7 based board using ISE. In my constraints file, the clock is defined like this: ## Clock signal NET "clk100mhz" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ NET "clk100mhz" TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 KHz HIGH 50%; I generated a signal that toggles on a rising edge off the clock, and on my logic analyzer it shows a frequency of 2.1kHz regardless of what I change the number to in the constraints file. I sample at >20 times whatever I set it to the frequency of the clock. Is there any reason that I'm reading 2.1kHz? If you need any more code/info just ask. Help would be appreiciated. |
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喜
此输出信号的频率取决于您正在使用的板载频率。 如果改变板载频率,您将能够改变切换信号的频率。 您在约束文件中更改的频率值将用于执行时序分析,它实际上不会改变您的板载频率。 有关更多信息,请参阅xilinx UG612 谢谢 shreyas -------------------------------------------------- --------------------------------------------尝试搜索你的答案 在发布新帖子之前在论坛或xilinx用户指南中发出问题。请注意 - 如果提供的信息解决了您的问题,请将答案标记为“接受为解决方案”。给予您认为有用的帖子给予荣誉(右边提供的星号) 并回复.---------------------------------------------- ------------------------------------------------ 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 hi, frequency of the this output signal is depended on the onboard frequency that you are using. you will be able to change frequency of toggling signal if you change on board frequency. frequency value that you are changing in constraint file will be used to perform timing analysis and it doesn't practically change your onboard frequency. for more information you can refer to xilinx UG612 thanks shreyas ---------------------------------------------------------------------------------------------- Try to search answer for your issue in forums or xilinx user guides before you post a new thread. Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query. Give Kudos (star provided in right) to a post which you think is helpful and reply oriented. ----------------------------------------------------------------------------------------------View solution in original post |
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喜
此输出信号的频率取决于您正在使用的板载频率。 如果改变板载频率,您将能够改变切换信号的频率。 您在约束文件中更改的频率值将用于执行时序分析,它实际上不会改变您的板载频率。 有关更多信息,请参阅xilinx UG612 谢谢 shreyas -------------------------------------------------- --------------------------------------------尝试搜索你的答案 在发布新帖子之前在论坛或xilinx用户指南中发出问题。请注意 - 如果提供的信息解决了您的问题,请将答案标记为“接受为解决方案”。给予您认为有用的帖子给予荣誉(右边提供的星号) 并回复.---------------------------------------------- ------------------------------------------------ 以上来自于谷歌翻译 以下为原文 hi, frequency of the this output signal is depended on the onboard frequency that you are using. you will be able to change frequency of toggling signal if you change on board frequency. frequency value that you are changing in constraint file will be used to perform timing analysis and it doesn't practically change your onboard frequency. for more information you can refer to xilinx UG612 thanks shreyas ---------------------------------------------------------------------------------------------- Try to search answer for your issue in forums or xilinx user guides before you post a new thread. Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query. Give Kudos (star provided in right) to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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您可以尝试使用MMCM并通过提供输入时钟生成所需的频率。
检查Artix-7 datsheet以了解需要考虑的MMCM输入和输出时钟规格 http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf 还请查看应该帮助您的时钟用户指南 http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf --Krishna 以上来自于谷歌翻译 以下为原文 you can try to use MMCM and generate the required frequency by providing the input clock. Check the Artix-7 datsheet for the MMCM input and output clock specifications which needs to be considered http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf also check the clocking user guide which should help you http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf --Krishna |
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