PAC1710/1720 I²C发送NACK

我已经使用了PAC1720上的设计多达5个部分，每一个设计（所有在同一个I2C总线）与I2C总线驱动在一个小FPGA（IGOO）使用我们在网上找到的一些VHDL I2C代码在400千赫。我们没有看到I2C总线的问题。似乎1710和1720是相同的，除了没有通道2和通道2在1710上注册。地址字节之后的NAK是没有响应。这意味着1710不识别地址。如果我调试这个，我会检查以下：-示意符号引脚匹配数据表-布局-足迹正确建立和连接正确的布局-电源是正确的电压和低噪音（可能是OK或信号）看起来不对劲。- I2C电阻足够强（我们使用1到4.7K取决于电压和客户数）-在I2C总线上发送的地址与电阻设置地址匹配，ADDRESSEL引脚上的电压是有意义的。在第一次设计中，我们确实有一些PAC1720的故障。我们正在测量输入电池电压（28伏）的电流。塞进电池后，Vdd在一段时间后出现了。最新的PAC1720（和我假设1710）数据表对此提出警告，并显示了一个电阻器/齐纳电路，以从输入功率VDD直到板电源可用。症状是连接到输入功率的通道上的读数差，但I2C总线继续正确操作。我知道这不是很大的帮助-祝你们好运。



      以下为原文

    I have used the PAC1720 on a number of designs with up to 5 parts per design (all on the same I2C bus) with the I2C bus driven at 400KHz by a small FPGA (Igloo) using some VHDL I2C code we found online. We've seen no issues with the I2C bus. It seems the 1710 and 1720 are identical except for the absence of channel 2 and channel 2 registers on the 1710.
A NAK after the address byte is the absence of a response. This means that the 1710 is not recognizing the address.
If I were debugging this, I would check the following:
   - schematic symbol pinout matches the datasheet
   - layout - footprint built correctly and connected correctly in layout
   - power is correct voltage and low noise (probably OK or the signals wouldn't look right).
   - I2C resistors are strong enough (we use 1 to 4.7K depending on voltage and number of clients)
   - address sent on I2C bus matches the resistor set address, and the voltage on the ADDR_SEL pins make sense.
 
We did have some failures of the PAC1720 on the first design. We were measuring current on input battery voltage (28V). After plugging in the battery, Vdd came up some time later. The latest PAC1720 (and I assume 1710) datasheet warns against this and shows a resistor/zener circuit to power Vdd from the input until board power is available. The symptom was bad readings on the channel connected to the input power, but the I2C bus continued to operated correctly.
 
I know this isn't a great deal of help - good luck

非常感谢你的回答！我检查了图纸和布局，一切都很好。但是，虽然在软件中设置了一个I.C调试循环，但我发现了实际问题：在数据表中，我忽略了PGE6中的“时间到第一次通信”，它表示，在读取或写入设备之前，Powerup之后必须有一个25Ms的延迟。因为我现在只想在启动时写一些配置寄存器，我没有注意到。我的坏，对不起！无论如何谢谢你！



      以下为原文

    Thank you very much for your Answer!
I checked the schematic and Layout - everything is just fine. But, while setting up a I²C Debug-Loop in Software, i found the actual issue: I overlooked the "Time to first Communications" on Page6 in the Datasheet, which says, there has to be a 25ms Delay after Powerup before reading or writing to the device. Since i only wanted to write some Config-Registers at Startup for now, i didn't noticed that. My bad, sorry!
Thank you anyway!

杰出的。我应该看看我的FPGA代码，确保我没有违反那个最短的时间。



      以下为原文

    Excellent. I should take a look at my FPGA code and make sure I'm not violating that minimum time.