vivado模拟中的字符串类型

嗨，我不认为Vivado有任何这样的系统任务。支持的系统任务很少被描述@ http://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-Design/2013x/Nexys4
/Verilog/docs-pdf/lab4.pdfhttp://www.origin.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug900-vivado-logic-simulation.pdf
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,
I don't think Vivado has any such system tasks.

Few of the supported systems tasks are described @
http://www.xilinx.com/support/documentation/university/Vivado-Teaching/HDL-Design/2013x/Nexys4/Verilog/docs-pdf/lab4.pdf

http://www.origin.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug900-vivado-logic-simulation.pdfThanks,Vijay
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谢谢您的回复。
你认为有没有其他方法来展示模拟过程？
使用modelsim进行vhdl或仿真会吗？
最好，
彼得



以下为原文

thank you for your reply.
 
Do you think is there any other way to show the process of simulation?
Does vhdl or simulating with modelsim will do?
 
 
best,
Peter

你好，
通过使用$ display，$ monitor或$ strobe显示在模拟过程中更改值的变量，可以逐步看到模拟过程。
这些系统任务也可用于在模拟期间显示文本。
在VHDL中，如果需要显示字符串，可以使用'image属性显示变量值，并使用assert-report语句显示字符串。
断言语句检查指定的条件是否为真，并相应地报告字符串。
要获得有关断言声明的更多详细信息，请查看此链接
http://vhdl.renerta.com/mobile/source/vhd00007.htm
问候，阿希什-----------------------------------------------
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以下为原文

Hello,
 
The simulation process can be seen stepwise by displaying the variables which are changing the value during simulation process by using $display, $monitor or $strobe. These system tasks can be used to display text as well during simulation.
 
In VHDL, if you need to display a string you can use 'image attribute to display value of a variable and assert-report statement to display a string. Assert statement checks that a specified condition is true and reports a string accordingly. To get further details regarding assertion statement please check this link
http://vhdl.renerta.com/mobile/source/vhd00007.htm   
Regards,
Ashish
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