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我是这个社区的新手,所以如果这种话题不符合该部分或者我滥用论坛,我会提前道歉。 我有一个项目,我需要实例化2000个分布式rams,由2000个数据文件初始化。 问题是,当我尝试使用iSim模拟我的系统的行为时,我遇到了这个错误: 错误:HDLCompiler:1030 表示无法找到第1024个ram的初始化文件,即使它位于工作目录中。 一个有趣的事情是,如果我总共使用511个rams,找到整个files.data集,一切都很好,它编译和模拟,但我需要2000个。 我真的尝试过这个问题,但这个问题似乎并不依赖于我的代码,所以我想知道是否存在可以使用的存储器总数的限制,或者如果这是我正在使用的套件ISE 14.4的错误。 我没有使用ipcore实例化rams,而是根据官方XST指南xst_v6s6,第7章中的说明设计了内存。谢谢你的帮助 以上来自于谷歌翻译 以下为原文 hi, I am new to this community so I apologize in advance if this kind of topic doesn't fit the section or if I am misusing the forum. I have a project in which i need to instantiate 2000 distributed rams, initialized by 2000 data files. The problem is that, when I try to simulate and thest the behavior of my system using iSim, I encounter this error: ERROR:HDLCompiler:1030 which says that the initialization file of the 1024th ram can't be found, even if it is in the work directory. An interesting thing is that if I use 511 rams in total, the whole set of files.data is found and everything is fine and it compiles and simulate, but i need 2000 of them. I tried literally everithing but this issue does not seem to depend from my code, so I was wondering if there is a limit of total number of memories that can be used or if that is a bug of ISE 14.4, the suite I am using. I have not used ipcore to instantiate the rams, instead i designed the memories according to what is stated in the official XST guide xst_v6s6, chap7 . thanks for your help |
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嗨,
您可以尝试使用设计中最大可能的DRAM(不会出现此错误)并查看实施后的利用率。 查看已使用了多少百分比的LUT资源。 但是,由于这是一个HDL编译器警告,我怀疑是否是这种情况。 尝试为设计目录提供更短的路径,并尝试在ISE 14.7中确保。 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi, Can you try with the maximum possible DRAM's in the design (which dont give this error) and see the utilization post implementation. See how much percentage of LUT resources have been utilized. However since this is a HDL compiler warning, i doubt if this is the case. Try to play around with giving shorter paths for the design directory and also try in ISE 14.7 to be sure. Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.View solution in original post |
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嗨,
请发布完整的错误消息。 您可以尝试在HDL中提供数据初始化文件的绝对位置,看看是否有帮助? 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi, Please post the complete error message. Can you try giving the absolute location of the data initialization file in the HDL and see if that helps? Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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我使用的设备是Zynq,xc7z020-2clg400。
公羊是2000,每个都有8位深度和100个元素。 我认为,如果它们对于lut rersources来说太多了,那么编译器无论如何都会起作用,但会发出一个警告,指出已经使用了> 100%的资源。 或者我错了?完整的错误是 错误:HDLCompiler:1030 - “I:/marco_matta/vhdl/matrixcalcpage/ram_lut.vhd”第29行:无法打开文件'LUT509REAL_di.data'.ERROR:模拟器:777 - 图书馆工作中顶级VHDL设计单元test19giu的静态细化 失败 我怎样才能给出文件的绝对位置?感谢lotmarco 以上来自于谷歌翻译 以下为原文 the device I am using is a Zynq, xc7z020-2clg400. The rams are 2000, each has a depth of 8 bits and 100 elements. I thought that if the they are too many for the lut rersources, the compiler would work anyway but giving a warning stating that >100% of resources were used. Or am I wrong? the complete error is ERROR:HDLCompiler:1030 - "I:/marco_matta/vhdl/matrixcalcpage/ram_lut.vhd" Line 29: Cannot open file 'LUT509REAL_di.data'. ERROR:Simulator:777 - Static elaboration of top level VHDL design unit test19giu in library work failed how can I give the absolute location of the file? thanks a lot marco |
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你好
8bits和100个元素不应该出现任何问题,你的ram_lut.vhd第29行有什么问题,你能提供快照吗? 另请查看此讨论 http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Core-Generator-Block-ROM-Virtex-5-XC5VSX50T/td-p/11160 -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索, 您可能会找到相关信息。请留下帖子 - “接受为解决方案”,如果提供的信息有用且回复,请给予赞誉 以上来自于谷歌翻译 以下为原文 Hi 8 bits and 100 elements should not casue any issue, what is there is in your ram_lut.vhd line 29, can you provide a snapshot? Please also check this discussion http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Core-Generator-Block-ROM-Virtex-5-XC5VSX50T/td-p/11160 --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented |
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编辑到我之前的帖子:公羊是2000,他们的WIDTH是8位,DEPTH是100
以上来自于谷歌翻译 以下为原文 EDIT to my previous post: the rams are 2000, their WIDTH is 8 bits and DEPTH is 100 |
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这里是。
这是我用来初始化记忆的功能。 以上来自于谷歌翻译 以下为原文 here it is. that's the function i used to initialize the memories. |
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嗨,
您可以在函数调用中给出绝对路径,如下所示 信号RAM:RamType:= InitRamFromFile(“C:/Users/User_name/Documents/test/rams_20c.data”); 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi, You can give the absolute path in the function call as shown below signal RAM : RamType := InitRamFromFile("C:/Users/User_name/Documents/test/rams_20c.data"); Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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嗨,
如果上述方法无效,请尝试修改第一行功能,如下所示 impure函数InitRamFromFile(RamFileName:in string)返回RamType isFILE RamFile:text在RamFileName中; 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi, If the above does not help, try modifying the first line of function as below impure function InitRamFromFile (RamFileName : in string) return RamType is FILE RamFile : text is in RamFileName; Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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嗨,我尝试了两种方法,但错误是相同的。谢谢
马尔科 以上来自于谷歌翻译 以下为原文 hi, I tried both ways but the error is the same. thanks marco |
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嗨马可,
你能分享测试用例吗? 谢谢, 迪皮卡。 谢谢,迪皮卡.---------------------------------------------- ---------------------------------------------- Google之前的问题 张贴。 如果某人的帖子回答了您的问题,请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子,考虑给它Kudos(左边的明星) 以上来自于谷歌翻译 以下为原文 Hi Marco, Can you share the test case? Thanks, Deepika. Thanks, Deepika. -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left) |
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