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嗨,
我想监视连接到microblaze的特定IP核的实际硬件信号。 我知道基地址,高地址,我要监视的寄存器偏移量,但是我无法连接JTAG,因为当我打开核心插入器时,我看到很多信号,触发器等,但我不知道 实际的硬件寄存器,映射到该地址。 所以我的问题是 - 处理器系统的具体地址如何映射到实际的硬件寄存器? 如何确定实际的硬件寄存器,该寄存器映射到处理器系统中的特定地址? 以上来自于谷歌翻译 以下为原文 Hi, I want to monitor actual hardware signal of the specific IP core, which is connected to microblaze. I know the base address, the high address, the register offset I want to monitor, but I cannot hook up JTAG, because when I open core inserter, I see a lot of signals, flip flops, etc. , but I do not know the actual hardware register, which is mapped to that address. So my question is - how the specific address from processor system is mapped to actual hardware register? How can I determine the actual hardware register, which is mapped to the specific address in processor system? |
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您将不得不对硬件进行一些调查。
打开.mhs文件(如果您在IPI中,则打开程序框图)并确定哪个外围设备位于该地址。 一旦知道了哪个外设,就必须深入研究代码才能找到实际的寄存器。 这不一定是一项微不足道的任务。也许有一种更简单的方法可以满足您的需求。 例如,我们有AXI Monitor核心,允许您观察总线上的事务,以确保您正在寻找正确的地址。您准备调试到底是什么? www.xilinx.com 以上来自于谷歌翻译 以下为原文 You will have to do a bit of investigation on the hardware. Open the .mhs file (or the block diagram if you are in IPI) and figure out which peripheral is at that address. Once you know which peripheral, you have to dig down into the code to find the actual register. It is not necessarily a trivial task. Maybe there is an easier way to do what you need. For example, we have AXI Monitor cores that allow you to watch transactions on the bus to make sure you are poking the right addresses. What exactly are you trying to debug?www.xilinx.com |
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好的,所以关于我们的定制板与斯巴达6的故事开始。我们使用带有RMII接口的以太网phy(KS8721BL),所以在fpga端有一个巨大的级联IP核(AXI总线 - > AXI-PLB桥 - >
xps ethernet lite - > mii_to_rmii IP)。 问题是,即使使用简单的“外围测试”C应用程序,我也无法从以太网phy接收“环回”帧。 通信似乎正在工作 - 在phy中成功启用了环回模式,但是在将帧发送到phy之后,应用程序无法接收任何内容(我已经通过在RXD总线上连接JTAG来检查它似乎是xps以太网 lite core正在接收来自mii_to_rmii核心的实际硬件信号。 因此,应用程序最有可能无法检测到它们(我猜)。 在核心数据表第14页中,指示地址寄存器的状态位(位31)(C_BASEADDR + 0x17FC)显示是否收到任何帧。 但那个位总是0 ......所以我想做的是找到保持该位值的实际触发器,并用JTAG监视它,如果它变为1 ......如果没有,我可能会 能够追踪所有这些似乎达到xps Ethernet Lite核心的信号消失的地方...... 我的方法很可能是错误的,所以我愿意接受任何建议。 以上来自于谷歌翻译 以下为原文 Ok, so the story begins about our custom board with spartan 6. We are using ethernet phy (KS8721BL) with RMII interface, so on the fpga side there is a huge cascade of IP cores (AXI bus -> AXI-PLB bridge -> xps ethernet lite -> mii_to_rmii IP). The problem is, that I cannot receive "loopback" frames from ethernet phy even using simple "peripheral test" C application. The communication seems to be working - the loopback mode is successfully enabled in the phy, but after transmitting the frame to the phy, application cannot receive anything (I've already checked by hooking up JTAG on RXD bus and it seems that the xps ethernet lite core is receiving actual hardware signals from mii_to_rmii core). So, it's most likely that the application cannot detect them (I guess). In core datasheet page 14 it's indicated that the Status bit (bit-31) of address register (C_BASEADDR + 0x17FC) shows if there is ANY frame received. But that bit is always 0...So what I wanted to do, is to find find the actual flip flop which holds this bit value, and monitor it with JTAG, if it ever turns to 1...If not, I might be able to track down where all these signals, which seem to be reaching xps Ethernet Lite core, dissappear... My approach most likely is wrong, so I'm open to any suggestions. |
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