三态缓冲区未按预期工作

嗨，
我写了一个非常简单的代码，其中FGPA从/向处理器读/写。
我使用以下代码推断数据总线的三态缓冲区（16位宽）。
- 推断IOBUF io_datah s_data_read
注意：“s_re_l_2q”是输出使能（in_oe_l）的注册版本。
我试图用FPGA读取FPGA（FPGA正在写入微处理器）。
并且，我用chipcope捕获了以下内容。
根据微处理器数据表，在输出使能的上升沿（当芯片选择为低电平时），微处理器应读取数据。
我相信所有时间都是正确的，并且有足够的余量，微处理器不会错过数据。
然而，奇怪的是，我不知道为什么当我从微处理器读取数据时，我得到数据0xC630，而我期待0xC430。
看起来微处理器正在写入FPGA而不是从FPGA读取。
但情况应该不是这样，而应该恰恰相反！
在推断三态缓冲区时，我是否设置了错误？
当我在planAhead中打开设计时，我可以看到“io_data”被认为是In / Out，这似乎是正确的。
想法，我做错了什么？
全局约束（offset-in / offset-out）是否可能导致此类行为？
任何帮助都很赞赏。
谢谢，
--Rudy



以下为原文

Hi,
I have wrote a very simple code, where FGPA read/writes from/to a processor.

I was using the following code to infer a tri-state buffer for the data bus (16-bit wide).

   -- Infering IOBUF
   io_datah    <=  s_data_write when (s_re_l_2q = '0') else "ZZZZZZZZZZZZZZZZ";
   s_data_read <= io_datah;

Note: "s_re_l_2q" is the registered version of the Output Enable (in_oe_l).

I made an attempt to read from FPGA with the microprocessor (FPGA is writing to microprocessor).

And, I captured the following with the chipscope.




Per microprocessor datasheet, at rising edge of the Output Enable (when chip-select is low), microprocessor should read the data.
I believe all the timing is correct, and there is enough margin that the microprocessor will not miss the data.
However, what is strange is that I don't know why when I read from microprocessor, I get the data 0xC630, whereas I was expecting 0xC430.
It seems like that microprocessor is writing to FPGA instead of reading from FPGA.
But that should not be the case, and it should be the exact opposite !!

Am I setting up something wrong, when infering the tri-state buffer ?
When I opened up the design in the planAhead, I can see that "io_data" is infered as In/Out, which seems correct.

And idea, what am I doing wrong? Could global constraint (offset-in/offset-out) be responsible for such behavior?

Any help is apprecited.

Thanks,
--Rudy