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我的问题很简单。 如何将数据输入GTX的发射器,以便自动处理IDLE,SF和EF? 也就是说,我如何只提供原始数据并声明一些启用信号? 向导的示例设计直接从帧生成器中的ROM仿真模型提供输入数据。 似乎ROM数据已经包含适当的IDLE,SF和EF序列; 但我需要给GTX我自己的数据。 据我所知,可能有两种选择: 1-(根据ug476,表3-30)使用MGT中的TXELECIDLE可配置驱动程序端口将线路置于空闲模式。 使用GTX向导时,不会将此端口带给用户,但更改它并不困难。 但处理Start Frame& 结束帧仍然是个问题。 2-(根据高速串行IO简单,图4-9,第65页),可以设计一个简单的FSM来管理数据,IDLE,SF和EF,如下所示。 这似乎并不困难,但我必须知道每个协议中哪些字符被选为IDLE,SF& EF。 GTX向导应该知道必要的序列,因为它列出了许多协议,所以我认为有一些更简单的方法可以做到这一点。 有没有其他方法可以让我的GTX运行? 谢谢。 以上来自于谷歌翻译 以下为原文 Hi My question is very elementary. How can I feed my data into a GTX's transmitter, so that IDLE, SF, and EF are automatically handled? That is, how can I provide just my raw data and asserting some enable signal? The example design of the wizard gives input data right from a ROM simulation model in the frame generator. It seems that the ROM data are already containing appropriate IDLE, SF and EF sequences; But I need to give the GTX my own data. As I know there may be two options: 1-(According to ug476, Table 3-30) Using TXELECIDLE configurable driver port in the MGT to put line in IDLE mode. This port is not brought to user when using GTX wizard, though it is not difficult to change it. But handling Start Frame & End Frames remain as question. 2- (According to High Speed Serial IO Made Simple, Figure 4-9, Page 65) a simple FSM can be designed to manage data, IDLE, SF and EF as shown below. This does not seem difficult, but I must know for each protocol which characters have been chosen as IDLE, SF & EF. GTX wizard should know necessary sequences because it lists many protocols, so I think there is some simpler way to do this. Is there any other method that I can have my GTX operational? Thanks. |
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不同之处在于SGMII是一个连续的载体系统。
以太网基于数据包。 所以概念略有不同。 对于没有以太网数据包的SGMII,如果我没记错的话,你需要发送IDLE序列4个10位字。 还有SFD和EFD之类的符号。 看看这个IP,它应该告诉你所有你需要知道的。 这不是您需要设计的,只需使用Xilinx免费提供的内容: http://www.xilinx.com/products/intellectual-property/DO-DI-GMIITO1GBSXPCS.htm - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 The difference is SGMII is a continuous carrier system. Ethernet is packet based. So the concepts are slightly different. For SGMII while there is no ethernet packet, you need to send IDLE sequence 4 10 bit words if I remember correctly. There are SFD and EFD like symbols too. Take a look at this IP and it should tell you all you need to know. This is not something you need to design, just use what Xilinx gives you for free: http://www.xilinx.com/products/intellectual-property/DO-DI-GMIITO1GBSXPCS.htm - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented.View solution in original post |
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> GTX向导应该知道必要的序列,因为它列出了许多协议,所以我认为有一些
>更简单的方法来做到这一点。 SF(帧起始),EF(帧结束)和IDLE的插入是协议级功能,而GTX是物理级块。 您需要在协议逻辑中对此进行编码。 您还将IDLE序列与电子IDLE功能混淆。 只要不需要发送数据就插入IDLE序列,并且通常包含时钟校正序列。 很少使用电气IDLE(我不确定SATA是否使用此功能)并将TXP / TXN压缩到与复位协议信号相同的电压电平,并且不在协议初始化之外使用。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 > GTX wizard should know necessary sequences because it lists many protocols, so I think there is some > simpler way to do this. The insert of SF (Start of Frame), EF (End of Frame), and IDLE are protocol level functions, while the GTX is physical level block. You need to code this within your protocol logic. You have also confused an IDLE sequence with an electrical IDLE function. An IDLE sequence is inserted whenever no data needs to be sent and usually contains a clock correction sequence. An electrical IDLE is rarely used (I'm not sure if anything other than SATA uses this function) and squashes the TXP/TXN to the same voltage level as a protocol signal for a reset and is not used outside of the protocol initialization. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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所以,正如我发现上面的原理图需要设计的逻辑然后连接到GTX的TX接口(我是对的吗?)。
rx控制器的输入是比特流。 我们寻找SF并在EF尚未收到时保存有效载荷(是吗?)并且伴随GTX向导的示例设计是物理层示例,而不是协议层? 这对我来说有点奇怪。 它在MGT周围生成包装器和FIFO。 对于物理层是否有必要? 在转换为纯有效载荷数据之后(即,在修整SF,EF和IDLE之后),最好放置FIFO。 谢谢 以上来自于谷歌翻译 以下为原文 So, as I found out a logic like the schematics above need to be designed and then connected to the TX interface of the GTX (Am I right?). The input to the rx controller is a bit stream. We look for SF and save the payload while EF has not received yet(Yes?) And the example design accomponying the GTX wizard is a physical layer example, not a protocol layer? It's a bit strange for me. It generates wrappers and FIFOs around MGT. For a physical layer is it necessary? FIFOs are better to be placed after conversion to pure payload data (that is, after trimming SF, EF and IDLE). Thanks |
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>我们寻找SF并保存有效载荷,而EF还没有收到(是吗?)
是的,这是链接初始化后的基本功能。 初始化,控制和对误码条件的响应需要其他逻辑。 >它围绕MGT生成包装器和FIFO 我没有太多使用MGT向导,但我不记得在设计中看到过织物FIFO。 MGT确实包括TX和RX弹性FIFO,但这是用于物理层同步和时钟校正的目的。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 > We look for SF and save the payload while EF has not received yet(Yes?) Yes, that is the basic functionality after link initialization. There would be other logic required for the initialization, control and responses to bit error conditions. > It generates wrappers and FIFOs around MGT I don't use the MGT wizards much, but I don't recall ever seeing a fabric FIFO created in the design. The MGT does include a TX and RX elastic FIFOs, but this are for physical layer synchronization and clock correction purposes. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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谢谢mcgett
我想我已经明白该怎么做了。 我应该开始编码,看看会出现什么。 谢谢 以上来自于谷歌翻译 以下为原文 Thanks mcgett I think I have understood what to do. I should start my coding and see what shows up. Thanks |
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嗨,
如果您对此帖有任何疑问,请告诉我们? 如果您找到问题的解决方案,请标记答案,以便对其他论坛用户有所帮助 谢谢,AnirudhPS:请将此标记作为答案,以防它有助于解决您的问题。如果帖子引导您找到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi, Let us know if you have any more queries on this post? Please Mark the answer in case you found the solution to your question so that it can be helpful for other forum users Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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我有点困惑。
我想我误解了IDLE,EF& SF概念。 我们举个例子: 在以太网中,每个数据包都有一个前导码,SFD,其他字段,& FCS。 因此以太网数据包看起来像: 55 55 55 55 55 55 55 D5 LL ... LL VV VV VV VV LL是其他领域,VV是FCS。 现在IDLE,SF,& 以太网的EF为55,(55 55 55 55 55 55 55 D5),& (VV VV VV VV)分别。 这些是协议层字符。 其他协议有自己的特征。 但: 在基于MGT的设计中,如上面的示意图(在之前的帖子中),我们需要物理层字符。 事实上,所有上述字符(包括55,D5,LL和VV)都是来自MGT观点的数据; 无论帧是什么,MGT都需要物理层IDLE,SF和& EF字符; 它们明显不同于(55,D5等)。 它们应该类似于(K29.7 K28.5),(K28.5 K28.5),(K28.0 D0.0)。 我在协议相关文档中找不到这样的字符。 例如,在Aurora协议的情况下,我搜索了pg074和ug775来查找SF,IDLE和EF字符,但是我没有成功。 谁能解释我的错误是什么? 谢谢 以上来自于谷歌翻译 以下为原文 I'm a little confused. I think I have misunderstood IDLE, EF & SF concepts. Let's give an example: In Ethernet, each packet has a Preamble, SFD, Other fields, & FCS. Thus an Ethernet packet looks like: 55 55 55 55 55 55 55 D5 LL ... LL VV VV VV VV LLs are other fields and VVs are FCS. Now IDLE, SF, & EF for Ethernet are 55, (55 55 55 55 55 55 55 D5), & (VV VV VV VV) repectively. These are Protocol Layer characters. Other protocols have their own characters. BUT: In an MGT-based design, like the schematics above (in the previous posts) we need Physical Layer characters. In fact all the above mentioned characters (including 55, D5, LL, & VV) are data from an MGT point of view; No matter what the framing is, an MGT needs Physical Layer IDLE, SF, & EF characters; and They are clearly different from (55, D5, etc). They should be something similar to (K29.7 K28.5), (K28.5 K28.5), (K28.0 D0.0). I cannot find such characters in protocol relevant documents. For example in the case of Aurora protocol I searched pg074 and ug775 to find SF, IDLE and EF characters, but I didn't succeed. Could anyone explain what my mistake is? Thanks |
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我认为你对问题中存在多个不同层次的事实感到困惑。
在FPGA和以太网PHY之间有一个MGT。 所有8b10b信令仅与MGT相关,与以太网完全无关。 你需要在8b10b数据之上加载以太网帧数据,即8b10b流有空闲时间(k29.7?),当它没空闲时你可以把以太网PREAMBLE + SFD + DATA + FCS作为有效载荷到8b10b流。你的初步问题是 “我如何将数据输入GTX的发射器,以便自动处理IDLE,SF和EF?”执行此操作的块称为MAC。 在FPGA模块和MGT之间,您需要一个带GMII输出的MAC,一个GMII到SGMII转换器,其中包含MGT。 然后,您只需与MAC通信,然后MAC生成PREAMBLE + SDF ...通过SGMII PCS等与MGT进行通信。 - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 I think you are confused by the fact that there multiple different layers in questions. Between the FPGA and the Ethernet PHY there is an MGT. All the 8b10b signalling is only relevant for the MGT and completely irrelevant for Ethernet. You need to load ethernet frame data on top of 8b10b data ie 8b10b stream has its own idle (k29.7?) when it's not idle you can put ethernet PREAMBLE+SFD+DATA+FCS as payload to 8b10b stream. Your initial question was "How can I feed my data into a GTX's transmitter, so that IDLE, SF, and EF are automatically handled? " The block which does this is called a MAC. Between your FPGA block and the MGT you need a MAC with GMII output, a GMII to SGMII converter which includes the MGT in it. Then you just talk to MAC which then generates the PREAMBLE+SDF ... which gets communicated to the MGT with the SGMII PCS etc.- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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谢谢muzaffer
你是对的。 我需要一个MAC来连接我的自定义逻辑。 实际上我已经设计了我的MAC,那里有一个GMII输出。 我的确切问题是GMII到SGMII转换器。 我需要在转换器内部安装一个MGT。 MGT有效载荷是PREAMBLE + SFD + ... + FCS。 但是MGT的IDLE,SF和EF是我的问题(假设使用了一些类似于上面原理图的架构)。 据我所知,你说这些序列与8b / 10b编码有关。 据我所知,8b / 10b是一种编码方案,有一组DATA符号和CONTROL符号。 CONTROL符号可用于构建协议,但8b / 10b本身没有IDLE,SF或EF。 事实上,IDLE,SF& EF与协议相关(此处为SGMII)字符,而不是编码相关(此处为8b / 10b)。 我对吗? 如果我是对的,我的问题是:什么是IDLE,SF& SGMII的EF序列? 如果我错了,请告诉我我的困惑。 非常感谢 以上来自于谷歌翻译 以下为原文 Thanks muzaffer Yes, you are right. I need a MAC to interface my custom logic. Actually I have already designed my MAC and there is a GMII output there. My exact problem is the GMII to SGMII converter. I need an MGT inside the converter. The MGT payload is PREAMBLE+SFD+...+FCS. But the MGT's IDLE, SF, and EF are my questions (Assuming that some architecture similar to the schematics above is used). As I understood, you said that these sequences are relevant to 8b/10b coding. As I know the 8b/10b is a coding scheme and has a set of DATA symbols and CONTROL symbols. CONTROL symbols could be used for building a protocol, but 8b/10b by itself has no IDLE, SF or EF. In fact IDLE, SF & EF are protocol relevant (SGMII here) characters, not coding relevant (8b/10b here). Am I right? If I'm right my question is this: What are IDLE, SF & EF sequences for SGMII? If I'm wrong please let me know my confusion. Thanks alot |
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不同之处在于SGMII是一个连续的载体系统。
以太网基于数据包。 所以概念略有不同。 对于没有以太网数据包的SGMII,如果我没记错的话,你需要发送IDLE序列4个10位字。 还有SFD和EFD之类的符号。 看看这个IP,它应该告诉你所有你需要知道的。 这不是您需要设计的,只需使用Xilinx免费提供的内容: http://www.xilinx.com/products/intellectual-property/DO-DI-GMIITO1GBSXPCS.htm - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 The difference is SGMII is a continuous carrier system. Ethernet is packet based. So the concepts are slightly different. For SGMII while there is no ethernet packet, you need to send IDLE sequence 4 10 bit words if I remember correctly. There are SFD and EFD like symbols too. Take a look at this IP and it should tell you all you need to know. This is not something you need to design, just use what Xilinx gives you for free: http://www.xilinx.com/products/intellectual-property/DO-DI-GMIITO1GBSXPCS.htm - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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谢谢muzaffer
实际上我正在寻找其他东西,但与它相配的IP核心源文件帮助了我很多。 我找到了我想要的东西。 同样对于其他协议,我理解要学习什么。 非常感谢 以上来自于谷歌翻译 以下为原文 Thanks muzaffer Actually I was looking for something else, but the IP core source files accomponied with it helped me much. I found what I was looking for. Also for other protocols I understood what to study. Thanks alot |
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你能告诉我你是使用ISE还是Vivado以及哪个版本?谢谢。
- 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 Could you tell me whether you are using ISE or Vivado and which version? Thanks.- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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我正在使用ISE 14.2。
你对Vivado而不是ISE有什么看法吗? 以上来自于谷歌翻译 以下为原文 I'm using ISE 14.2. Do you have some point regarding Vivado instead of ISE? |
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