只使用一个通道的DAC有可能以预期采样频率的两倍工作吗？

显示你的代码，也许



      以下为原文

    Show your code, maybe

也许你更新了2次，左边和右边？猜猜看，你不用水晶做奥克斯吗？



      以下为原文

    Maybe you update 2 times, left & right ?, just a guess.
Dont u use crystal for aux ?

//////////////////////////////////////////////////////////////////////////////////////////////1/2，ClDIV= 1:128；/DOS= 1:1，FRC= 1:1，N2＝2，N1＝4 PLLFBD＝75；/除数m＝77；m＝PLLFBD +2 ACLKCON= 0x0700；//OSC Del DAC：SELACLK＝0，AUX OSC禁用，APSTLSCR & Gn；n除以1，AS您好，这里是：///////////////////////////////////////////////////（？）RCSEL＝0μSuxTiNTIN WORKESEOSCCONH（0x03）；DC1Lee＝0；//关闭DAC INT。当与DMA一起使用时，DAC不能生成INTs DAC1CONC= 0x2102；//OFF，2补，除数CKDIVI＝3（DACFDIV＝2）100KSPs DAC1STAT＝0x8505；/ /左通道，右。= 1）AC1DFLT＝DAcDebug；/DAC1LIF＝0；DAC1CONTITE；DAC1CONTITE；DAC1CONTITE；////////////////////////////////////////////////DMA段外，int LutB [LutbjLe++] 1，Apple（1）；（或（主）C DMA0CONTITY；Chen＝0；IEC0BIT。DMA0IE＝0；IPC1通道关闭，中点关闭，如果FIFO空，位。DMA0COIP＝7；DMA0CONC＝0x2000；//字大小，写入外围设备，INT在完整传输块，正常操作，具有后增量，连续模式和乒乓关闭DMA0Req＝0x00 4F；/INT由DAC1L DMA0STATA＝Y-BuuthTiNoDMACOBUP（＆LUTB〔1〕）；/ /连接LUTB阵列DMA0PAD =（无符号未登录）LDAT-DMA0CNT＝LutbxLe-1；//LutbjLe是100个样本，正弦周期IFS0BIT.DMA0IF＝0；DMA0IE＝1；；/激活INT//////////////////////////////////////////////／其他：γ定义GeNa启动DMA0CONTITE，Chen＝1；DMA0ReqBist.For＝1；//Ge宏开始生成。DAC1LDAT；// DAC1AC1L ISR和中断不存在，因为不是NeDeD.DMA0ISR只停止生成（DMA0BITE，Chen＝0），并事先用用户标记谢谢。



      以下为原文

    Hi, here is:
 
////////////////////////////////////////////////// OSCILLATOR SECTION
    // PLL (Using 8MHz XTAL)

    CLKDIV=0x7002;                      // DOZE=1:128, DOZE OFF, FRC=1:1, N2=2, N1=4  
    PLLFBD=75;                             // Divisor M=77, M=PLLFBD+2
    ACLKCON=0x0700;                   // OSC del DAC: SELACLK=0, Aux Osc disabled, APSTSCLR-> N divide by 1, ASRCSEL=0

    __builtin_write_OSCCONH(0x03);
    __builtin_write_OSCCONL(OSCCON | 0x01);

    while((OSCCONbits.OSWEN==1) | (OSCCONbits.LOCK != 1));
    OSCCONbits.CLKLOCK=1;
 
//////////////////////////////////////////////// DAC SECTION
    IEC4bits.DAC1LIE=0;           // Shut off dac INT. When used with DMA, DAC must not generate ints  
    DAC1CON=0x2102;             // OFF, TWO's complement, Divisor CLKDIV=3 (DACFDIV=2) 100ksps
    DAC1STAT=0x8505;            // Left Channel ON, Right Channel OFF, Midpoint OFF, INT if FIFO empty,
    DAC1DFLT=DACDEFAULT;    // default value
    IFS4bits.DAC1LIF=0;        
    DAC1CONbits.DACEN=1;
 
////////////////////////////////////////////// DMA SECTION
 
    extern int lutb[LUTB_LEN+1]__attribute__((space(dma)));   // in main.c
    DMA0CONbits.CHEN=0;
    IEC0bits.DMA0IE=0;
    IPC1bits.DMA0IP=7;
    DMA0CON=0x2000;                                        // Word size, Write to peripheral, INT when complete transfer block, Normal operation, with Post-increment, Continuous mode and ping-pong off
    DMA0REQ=0x004F;                                        // INT by DAC1L
    DMA0STA=__builtin_dmaoffset(&lutb[1]);         // Connect lutb array
    DMA0PAD=(volatile unsigned int)&DAC1LDAT;   // with DAC1LDAT
    DMA0CNT=LUTB_LEN-1;                                 // LUTB_LEN is 100 samples, a sine period
    IFS0bits.DMA0IF=0;          
    IEC0bits.DMA0IE=1;                                       // Activate INT
 
////////////////////////////////////////////////////// others:
#define GEN_START   DMA0CONbits.CHEN=1;DMA0REQbits.FORCE=1; // Macro to start generation
 
DAC1L ISR and interrupt does not exists because isn't needed.
DMA0 ISR only stops generating (DMA0bits.CHEN=0) with a user flag
 
Thank you in advance.
 
R.

我使用的是初级XTAL。配置PLL为38，5 MIPS（接近40 MIPS的最大DSPIC），并设置正确的分频器，我可以得到100kSPS（正好100，28 kSPS）。



      以下为原文

   
I am using primary XTAL. Configuring PLL for 38,5 MIPS (near 40 MIPS maximun of this dsPIC) and set dividers correctly, can I get 100ksps (exactly 100,28 ksps).

在这个论坛上已经有几篇关于这一点的文章了，底线是这样的：在这个芯片的文档中有一个长期存在的问题（最后的数据表修订日期是2012），微芯片已经指出，它们将在下一个版本中进行更正。文档的。（我讨厌恶作剧，但不要屏住呼吸！）[开始编辑]见我稍后的帖子以修正下面的讨论。我很想删除剩下的东西，但这是一个令人尴尬的提醒，在重新发布旧数据之前要重新检查旧数据。抱歉！[/EddieEd]，即寄存器9－5中的SELACLK位的描述表示DAC时钟将是PLL输出。（图9-2中的FVCO）停在那里！在括号中忽略FoSC。或者，（精神上）敲击它并用FVCO替换它。完整的定时信息为您的设置：您的FVCO等于8 MHz / 4×77＝154 MHZTED，因为您已经设置PLLPOST除以2，Fosc为77 MHz，对于指令频率为38.5 MIPSSO，如果实际的APLL输入频率是两倍W。你在计算中使用的，这可以解释为什么DAC输出信号是你期望的频率的两倍。我还没有真正看过你的DAC代码（实际上你还没有发布足够的信息让我们知道），但这就是我的印象。我以前在一个小测试项目中使用过这个芯片，并且观察到了和你一样的问题：输出频率是我预期的2X。当我改变我的样本频率计算使用FVCO，一切都很好。底线：回答你的第一个帖子的问题，没有什么特殊或不同的，无论你使用一个渠道或两者兼而有之。你必须让采样频率正确（不感谢数据表）。问候，戴夫。



      以下为原文

    There have been a few posts about this on this forum over the years and the bottom line is this:
 
There is a long-standing problem with nomenclature in the documentation for this chip (Last Data Sheet revision is dated 2012)  Microchip has indicated that they will make a correction at the next release of the documentation.  (I hate to be snarky-snide, but---don't hold your breath!)
 
[/Begin Edit]
See my later post for correction to the discussion below.  I am tempted to delete the remaining stuff, but it serves me as a an embarrassing reminder to re-check old data before posting later stuff.
 
Sorry!
[/End Edit]
Namely, the description of the SELACLK bit in Register 9-5 says that the DAC clock will be the PLL output.  (That's Fvco in figure 9-2.)  Stop right there!  Ignore the Fosc in parentheses.  Or, (mentally) strike it out and replace it with Fvco. 
 

 
Complete timing information for your setup:
Your Fvco is equal to 8 MHz / 4 * 77 = 154 MHz
 
Then, since you have set PLLPOST to divide by two, Fosc is 77 MHz, for an instruction frequency of  38.5 MIPS
 
So if the actual APLL input frequency is twice what you used in your calculations, that can explain why the DAC output signal is twice the frequency you expect.  I haven't actually looked at your DAC code very much (actually you haven't posted enough for us to know for sure), but that's my impression.
 
I used this chip some time ago in a little test project, and observed the same problem as you: Output frequency was 2x what I expected.  When I changed my sample frequency calculations to use Fvco, all was well.
 
 
Bottom line: To answer  the question of your first post, there is nothing special or different whether you use one channel or both.  You just have to get the sample frequency correct (no thanks to the Data Sheet).
 
 
Regards,

Dave
 

嗨，戴夫，谢谢你的完整解释。奇怪的是，DAC在两个时钟频率下工作良好。2X覆盖（哦，是的，工作！）当生成方波时，可以看到在100kHz的主频下FIR滤波器的时间响应。在SUNC响应中，我们有f*Loop[n]＝（（2n+1）/2）·fs，这意味着第一个波瓣（占主导地位）在FS/2，与你的假设相匹配！结论…你说得对！最好的问候，罗杰



      以下为原文

    Hi Dave, thank you for your complete explanation.

It's strange that DAC works fine at twice clock frequency. 2x overcloking (oh yeah, and works!).

When I am generating square waves, can see the FIR filter time response at 100kHz predominant frequency.

In a sinc response, we have f_lobe[n]=((2n+1)/2)·fs, that means 1st lobe (predominant) is at fs/2, that matches woth your supposition!

Conclusion.. your are right!
 
Best regards,
 
Roger

进一步的测试表明，我的叙述是错误的。事实上，PLLPOST＝0（Fvco输出除以2给系统时钟，Fosc），DAC输入时钟等于FVCO值。然而，事实证明，PLLPOST的不同值确实影响DAC输入频率。E值的FVCO，改变PLLPOST到1（Fvco输出除以4）给出了不同的DAC输入频率。（我通过在DAC中断服务程序中放置一个LED开关来测试）。当然，DAC频率输出依赖于来自DAC输入频率的采样频率，所以这些误差也是错误的。此外，当将PLLPOST转换为3（Fvco输出除以8）时，得到不同的DAC采样频率（和输出频率）。DAC输入频率等于FoSC时间2。我在微芯片文档的任何框图中没有看到或显示任何这样的信号，但这就是我对这个特定芯片的看法。总结：指令频率，FCY总是被Fosc划分为2，如文献所记载的那样。这受PLLPASDAC输入频率的影响（用SelaCLK＝0）总是Fosc乘2。这受PLLPOST的影响，与数据表中的描述和家庭参考手册中的（不同但不正确的）语句相矛盾。因此，对数据表的寄存器9－5中的描述进行校正可以如下：如果这是错误的，我将非常感激。来自任何人的启示。任何人。我为我以前的帖子的错误陈述道歉。问候，戴夫。



      以下为原文

    Further testing shows my narrative was incorrect.
 
It is, indeed, true that with PLLPOST = 0 (Fvco output divided by 2 to give system clock, Fosc), the DAC input clock is equal to the Fvco value.
 
However...
It turns out that different values of PLLPOST definitely affect the DAC input frequency.
 
With same value of Fvco, changing PLLPOST to 1 (Fvco output divided by 4) gives a different DAC input frequency.  (I tested by putting an LED toggle in the DAC interrupt service routine).  Of course, DAC frequency outputs depend on the sample frequency derived from the DAC input frequency, so those are also wrong.
 
Furthermore, when I changed PLLPOST to 3 (Fvco output divided by 8) I get a different DAC sample frequency (and output frequencies).
 
New Conclusion...
My observations are that the DAC input frequency is equal to Fosc times 2.  I don't see any such signal mentioned or shown on any block diagrams of Microchip documentation, but that's the way I see it for this particular chip.
 
Summary:

• Instruction frequency, FCY is always Fosc divided by 2, as documented.  This is affected by PLLPOST
  
• DAC input frequency (with SELACLK = 0) is always Fosc multiplied by 2.  This is affected by PLLPOST, in contradiction to description in the Data Sheet and to a (different but still incorrect) statement in the Family Reference manual.
  

So a correction of the description in Register 9-5 of the data sheet can go like this:
 

 
If this turns out to be wrong, I would appreciate any enlightenment from anybody.  Anybody at all.
 
 
I apologize for the incorrect statements of my previous post.
 
 
Regards,

Dave

不要担心我的朋友。很显然，Microchip的振荡器部分对此有一个错误，因为暴露的计算与我们的测试不匹配。我们测量的DAC频率是预期的两倍，然后…FS＝4·fCy/（256·N·CLKDIV）：4∶38，5MHz／（256·2·3）＝100，26kSPS，与查找表期和SUNC（x）时间响应匹配。我去通知Microchip有关。最好问候戴夫，谢谢您的时间。罗杰。



      以下为原文

    Dont' worry my friend.
 
It's clear that microchip's oscillator section of this micro has a mistake about this, because exposed calculations does not match with our tests. We has measured DAC frequency is twice than expected, then... Fs=4·Fcy/(256·N·CLKDIV)
 
In my case: 4·38,5MHz/(256·2·3)=100,26ksps, that matchs with Look-Up Table period, and SINC(x) time response.
 
I go notify microchip about that.
 
Best regards Dave, and thank you for your time.
 
Roger.

几年前我和这一部分合作过，不记得有什么问题。所以我看了我的数据表（Rev E，2011），它正确地使用FVCO在图9-1和寄存器9－5上。



      以下为原文

   
 
I had worked with this part years ago and didn't remember any issues with clocking the DAC.  So I looked at my data sheet (Rev E, 2011), and it correctly uses Fvco on both Figure 9-1 and Register 9-5.

我不喜欢重复我自己，但是我最近用一个DSPIC33 FJ128GP802显示：ADC的输入频率总是等于FoSC * 2（Where Fosc是PLL输出分配器的输出）。在数据表（DS7029 2G）的寄存器中，寄存器9－5的描述表明，用SelaCLK等于零，Fosc PR。为辅助时钟分频器提供源时钟。我无法访问数据表的早期版本；也许Rev G是错误的尝试纠正以前的错误陈述，但他们仍然拧紧了PooCH。所以这里的交易：如果PLLPOST＝0B00，因此Fosc等于FVCO／2，我们正好“得到”正确的数字答案“。NG到您所引用的数据表：由于FVCO等于FoSC * 2，ADC输入频率的值实际上等于FLCO的这个PLLPOST值的值。这不幸的事件导致我在第一篇文章中的错误陈述，因为那时我还没有用PLLPOST的其他值进行测试。我后悔写了这个错误的结论。所以这里的新政：考虑以下情况，我使用相同的FVCO值，但改变PLLPOST：如果PLLPOST等于0B01，使Fosc等于FVCO／4，ADC输入频率现在等于FoSC＊2的新值，而这i如果PLLPOST等于0B11，使Fosc等于FVCO／8，ADC输入频率现在等于FoSC＊2的这个新值，并且不等于FVCO。



      以下为原文

     
I hate to repeat myself, but my recent experiments with a dsPIC33FJ128GP802 show: ADC input frequency is always equal to Fosc * 2  (Where Fosc is the output of the PLL output divider.)
 
The description of Register 9-5 in Rev G of the data sheet (DS70292G) says that, with SELACLK equal to zero, Fosc provides the source clock for the Auxiliary clock divider.  I don't have access to the earlier versions of the data sheet; maybe Rev G was a misguided attempt to correct previous misstatements, but they still screwed the pooch.
 
So here's the Deal:
 
If PLLPOST = 0b00, so that Fosc is equal to Fvco / 2 we 'just happen' to get the "right numerical answer" according to the data sheet you quoted: Since Fvco is equal to Fosc * 2, the value of the ADC input frequency is, indeed, equal to the value of Fvco for this value of PLLPOST.  This unfortunate happenstance led me to my wrong statements in my first post, since at that time I had not tested with other values of PLLPOST.  I regret having written that incorrect conclusion.
 
So here's the New Deal:  Consider the following cases where I used the same value of Fvco but changed PLLPOST:
 

• If PLLPOST is equal to 0b01 so that Fosc is equal to Fvco / 4,  the ADC input frequency is now equal to the new value of Fosc * 2, and this is NOT equal to Fvco.
  

• If PLLPOST is equal to 0b11 so that Fosc is equal to Fvco / 8, the ADC input frequency is now equal to this new value of Fosc * 2, and is NOT equal to Fvco.
  

 
Regards,

Dave
 

这里是Rev E数据表：HTTP://www. xARGS.COM/PIC/33 FJXXGPX02-4.PDF



      以下为原文

    Here's the Rev E datasheet: http://www.xargs.com/pic/33fjXXgpX02-4.pdf

殿堂。当然，在该版本中，FVCO显示了Fosc，但在Rev G（更新）出现Fosc。我猜是微芯片上的错误，还有一个关于DAC的事情。有人做过输出差动电压测试吗？我发现差分输出有点不平衡。V0DAC1LPVY-DAC1LN＝6MV，在0x000两个互补值。这是典型的1,15V范围内的5,6%的偏移，它也具有明显的时间/温度漂移。因为最后一次偏移不能精确补偿。



      以下为原文

    Hi temples. Certainly in that revision Fvco is shown where Fosc, but in Rev G (newer) appears Fosc. A mistake from microchip I guess.
 
An other thing about DAC. Somebody has make tests with output differential voltage? I found Differential outputs are a bit unbalanced. V_DAC1LP-V_DAC1LN=65mV at 0x0000 TWO's complement value. That is 5,6% offset in the typical dinamic range of 1,15V. It have time/temperature clearly visible drift too. Because this last, offset cannot be compensated with precision.
 
Regards,

根据我用DSSPIC3FJ128GP802的测试，这两个都是不正确的，正确的说法是FoSC * 2。正如我提到的一个时间或三，如果你“恰巧”使用PLLPOST＝2，那么FVCO的数值等于FoSC＊2，所以你可能会被愚弄到F。VCO是正确的，但事实上，我已经测试过：相同的FVCO给出了不同的DAC采样频率和不同的PLLPOST值。有没有人听我这么说？（参见脚注）数据表中的规范对于差分输出值、偏移量等都非常松散。我猜这就是为什么Microchip指出，这个DAC只用于音频应用，而不是用于控制应用。即使数据表中的值较低（标称1.15 V PO）。输出电压可在1至2伏特范围内；标称-1.15的负输出可在2至1伏特范围内。在该芯片的勘误表中有一段是状态，换句话说，如果输出电平精度很重要，你可以期望使用外部电路来修整输出值。对于消费类音频应用程序，称为音量控制。如果你正在想一个精密的测试仪器，那么这是另一个故事……DaveFootnote，不管怎样。



      以下为原文

   
According to my tests with a dsPIC33FJ128GP802, both are incorrect; the correct statement is that it is Fosc * 2.
 
Well, as I have mentioned a time or three, if you "just happen" to be using PLLPOST = 2, then the numerical value of Fvco is equal to Fosc * 2 so you might be fooled into thinking that Fvco is correct, but, in fact, I have tested this:  The same Fvco gives different DAC sampling frequency with different values of PLLPOST.  Is anyone else tired of hearing me say this?  (See Footnote.)
 
 
The specifications in the data sheet are quite loose with respect to differential output values, offset, etc.  I guess that's why Microchip states that this DAC is intended for audio use only, not for control applications.
 
Even with the loose values in the data sheet (nominal 1.15 V positive output can range from 1 to 2 volts; nominal -1.15 negative output can range from -2 to -1 volts) there is a section in the Errata for this chip that states

 
In other words, if output level precision is important you can expect to use external circuitry to trim the output values.  For a consumer audio application, that's called a Volume Control.  If you are thinking of a precision test instrument, well that's another story...
 
 
Regards,
 
Dave
 
Footnote:
   Over and out.

好吧，戴夫。我知道Microchip说“只是为了音频应用，而不是为了控制”。我的应用程序基本上像音频，这个DAC符合我的要求，只需补偿代码的偏移量，并使用ADC来读取模拟输出。我的帖子只是为了讨论这个问题，并要求更好的想法。请看，罗杰。



      以下为原文

    Okay dave. I did knows microchip said "Just for audio applications, not for control". My application is like audio essentially and this DAC meets my spects just compensating offset by code and using a ADC for readback analog output.
 
My post is just for discuss about that and request for better ideas.
 
regards,
 
Roger

计算公式S.4DMA-CH从SPI到内存和内存到双缓冲的DAC，多路复用时有2个通道。其他芯片是有能力的，类似于ADC的工作方式。当你传送超过1个频道时，你必须把数据复用成一个快速的提取功能，可以把通道放在为DAC准备好的单独的存储区中。它可以处理44.1KHz的立体声。这很快，考虑到我是森迪。NG样本数据、通道数据和大约10个VAR，每一行至少有80Car的UART同时触发LED。没有使用DMA，但它可以完成。同时从FAT16/FAT32读取。这是多么令人心旷神怡，电线是如此的小，但却能导电，然后你会看到含有50B晶体管的芯片。100的大脑有100B神经元，运行在1MZ。所以我的英特尔4GHz CPU比我的大脑快4000倍，但假设3B晶体管是智能的33倍。（理论上）



      以下为原文

    #ifdef EXTERNAL_CRYSTAL
#define FIN 10000000
#define N1 2 //.8 - 8MHz
#define M 32  //100-200Mhz
#define N2 2
#else
#define FIN 7370000L
#define N1 8    //921,250
#define M 173   //159,376,250
#define N2 2    //79,688,125
#endif
#define FOSC (FIN/N1*M/N2)
#define FVCO (FIN/N1*M)
#define FCY (FOSC/2)
#define SAMPLE_RATE 44100L
#define DACFREQ (SAMPLE_RATE*256L)
#define DACDIV (FVCO/DACFREQ)
 
Calculating the formula's.
 
4 dma ch's to transfer from spi to memory and memory to dac with double buffering.
2 channels when mutiplexing.  Other chips are capable, similar to the way the adc works.
 
When you transfer more than 1 channel you have to multiplex the data with a fast extraction function that can put the channels into separate memory areas ready for the dacs.
 
It can handle 44.1KHz in stereo.
This is fast considering I was sending sample data, channel data and about 10 vars with at least 80char's per line to the uart at the same time and triggering leds.
Didn't use dma on that but it could have been done.
 
At the same time reading from fat16/fat32.
 
These chips are quite impressive really considering what todays chips can do is mind blowing.
And how the wires are so small and yet capable of conducting electricity.
Then you read about chips containing 50B transistors. and 100 cores
 
The brain has 100B neurons and runs at 1Mz.
So my Intel 4GHz CPU is 4000 times faster than my brain but 33 times less smart assuming 3B transistors. (In theory)