当FPGA满了？

从您设备的利用率来看，您绝对可以为您的设计添加更多逻辑。
这取决于您的要求。
我绝对可以看到BRAM和DSP用于dsp /视频应用。
您还可以通过在ISE MAP属性中使用“将切片逻辑映射到未使用的块RAM”来进一步尝试减少切片。



以下为原文

From your device's utilization, you can definitely add some more logic to your design. This would depend on your requirement.
I can definitely see BRAMs and DSPs being used for dsp/video applications. You could also further try to reduce the slice usgae by using "Map Slice Logic into Unused Block RAMs" in ISE MAP properties.

您还可以通过在ISE MAP属性中使用“将切片逻辑映射到未使用的块RAM”来进一步尝试减少切片。
你能举一个这个开关的例子吗？
我从未见过它有任何影响（我用Spartan 6设计）。
实际上，这个帖子表明它没有任何效果。
对于OP：它还取决于路由的复杂性以及IO的广泛程度。
您可能只有26％的注册用量，但由于密集路由而无法访问它们，因此它们实际上已丢失。
您可能需要在一定程度上对您的设计进行平面布局，以便真正了解您可以在哪里放置更多东西。
此外，它取决于您的约束。
如果您不限制工具使用设备的一小部分区域，那么工具将尽最大努力满足您提供的限制（如果有的话）。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

You could also further try to reduce the slice usgae by using "Map Slice Logic into Unused Block RAMs" in ISE MAP properties.
 
Can you provide an example of this switch in action? I have never seen it have any effect at all (I hav designed with Spartan 6). In fact, this thread here implies that it has NO effect whatsoever.
 
To the OP: It also depends on the complexity of routing and how widespread your IO is. You may have only 26% register usage but it you can't access them due to dense routing then they're effectively lost. You'd probably need to floorplan your design to some degree to really see where you can fit more things in.
 
Additionally, it depends on your constraints. If you don't constrain the tools to use a small area of the device then the tools will do whatever is easiest to meet the constraints you provide (if any).
----------
"That which we must learn to do, we learn by doing." - Aristotle

谢谢您的回复。
我有一个带有很多axi总线和外围设备的XPS项目。
我想添加另一个MicroBlaze。
我从未使用过布局规划限制（也没有2个MicroBlazes），我会尝试



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Thank you for your reply. I have an XPS project with a lot of axi buses and peripherals. I would add another MicroBlaze.
I never used floorplan constraints (never had 2 MicroBlazes also), i will try

我想真正的答案是“吮吸它并看到”。
试一试，看看Map和PAR工具告诉你什么。
有节省空间的技巧，但我会尝试利用SmartXplorer或PlanAhead提供的并行运行（也许Vivado也允许这样做，我不知道）。
在相关的说明中 - 严格来说，AXI不是总线而是互连，使用了多少资源取决于您是否具有完整的交叉开发实现（高吞吐量，高资源使用）或共享总线（像PLB一样;
较低的比较吞吐量，较低的资源），更不用说AXI PCIe桥的同步/异步接口（如果有的话），因此，根据您的吞吐量要求，摆弄AXI设置也可以帮助资源利用。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

I guess the real answer is "suck it and see". Try it out and see what the Map and PAR tools tell you. There are tricks to save space but I would try to take advantage of either SmartXplorer or the parallel runs that PlanAhead offers (maybe Vivado allows this too, I don't know).
 
On a related note - AXI, strictly speaking, isn't a bus but an interconnect and how much resources is used depends on whether you have a full cros***ar implementation (high throughput, high resource usage) or a shared bus (bit like PLB; lower comparative throughput, lower resources), not to mention the synchronous/asynchronous interface to the AXI PCIe Bridge (if you have one) so, depending on your throughput requirements, fiddling around with the AXI setup can help resource utilisation as well.
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"That which we must learn to do, we learn by doing." - Aristotle