如何编写VHDL代码

另一种方法可能是将4位输入转换为十进制，然后实现a
十进制乘数...
-  Gabor



以下为原文

Another method may be to convert the 4-bit inputs to decimal and then implement a
decimal multiplier...
-- Gabor

我欺骗和谷歌搜索可合成的二进制到BCD转换器，我很高兴...
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

I cheated and Googled for a synthesizeable binary-to-BCD converter and am very happy with it...

------------------------------------------
"If it don't work in simulation, it won't work on the board."

joelby，
我认为Gabor和rcingham正在做这个家伙的家庭作业是卑鄙的。
我很震惊......震惊了！
否则我建议使用256x12 Block RAM进行乘法和BCD转换。
但我不会，因为我高于这种事。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

joelby,
 
I think it is despicable that Gabor and rcingham are doing this fellow's homework assignment.  I am shocked... SHOCKED!
 
Otherwise I would have suggested using a 256x12 Block RAM for the multiply and BCD conversion.  But I won't, because I am above that sort of thing.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

哈哈，我误读了我的家庭作业要求。
我应该显示十六进制值而不是十进制值。
我已经知道了。
我现在还有其他问题，我似乎无法找到解决问题的方法。



以下为原文

Haha, I misread my homework assignment's requirements.  
 
I am supposed to show the Hex value not the decimal value. 
 
I figured that out already.  I have other problems now which I can't seem to figure out a way to trouble shoot.  

我需要帮助开发用于使用格林函数解决3D亥姆霍兹波动方程的VHDL代码。我正在接受文档。
使用GREEN.docx 21 KB解决3D Helmholtz方程



以下为原文

I need help for developing VHDL code for the solution of 3D Helmholtz wave equation using Green's function.I'm attatching the doc .
            SOLUTION OF 3D HELMHOLTZ WAVE EQUATION USING GREEN.docx ‏21 KB

如果有人能帮我解决这个问题请
开发同步（时钟）2位，模16二进制编码十进制（BCD）递增计数器的行为VHDL模型。
计数器应从0到15计数，然后再从0继续。
计数器应具有有效的高CLR信号，以便随时将其内容重置为0。
计数器的状态应显示在Nexys 2板的7段显示模块上。
CLK和CLR信号都应分别映射到按钮。
注意：当使用来自布什按钮的信号CLOCK为电路计时时，必须添加语句NET“CLOCK”CLOCK_DEDICATED_ROUTE = FALSE;
到您的.ucf文件。
您应该使用FPGA，7段显示器和Nexys 2板上的按钮来实现此计数器.a）分别为您的设计提供.vhd和.ucf文件的硬拷贝.b）映射您的电路
通过运行实施步骤，到位于FPGADevelopment Board上的Xilinx FPGA芯片。
在此之前，将UserConstraints（.ucf）文件添加到项目中，以便为您的设计进行正确的引脚分配。
Nexys 2 Board的Master .ucf文件可通过ClassWeb页面获得。
但是，您需要编辑它以仅保留您的.vhd文件中定义的那些信号。
仅转入设备利用率并分别使用Pad Report.Email的引脚分配部分：mass1311@yahoo.com



以下为原文

If any one can help me to solve this problem please 
Develop a behavioral VHDL model of a synchronous (clocked) 2-digit, modulo-16 binary-coded-decimal (BCD) up counter. The counter should count from 0 up to 15 and then continue from 0 again. The counter should have an active high CLR signal to reset its contents to 0 at any time. The counter's state should be displayed on the 7-segment display module of the Nexys 2 Board. Both the CLK and the CLR signals should be mapped to pushbuttons, respectively. Note: when using signal CLOCK from a bush button for clocking your circuit you must add the statement NET "CLOCK" CLOCK_DEDICATED_ROUTE = FALSE; to your .ucf file. You should implement this counter using the FPGA, the 7-segment display and push-buttons on your Nexys 2 Board.
a) Turn in a hard copy of the .vhd and .ucf files for your design, respectively. 
b) Map your circuit to the Xilinx FPGA chip that is located on your FPGA
Development Board by running the Implement step. Before doing so, add a User
Constraints (.ucf) file to your project to make proper pin assignments for your
designs. The Master .ucf file for the Nexys 2 Board is available through the Class
Web Page. However, you need to edit it to keep only those signals that are defined in
your .vhd file. Turn in only the device utilization and used pin assignments
sections, respectively, of the Pad Report. 
Email : mass1311@yahoo.com

zgd2449写道：
如果有人能帮我解决这个问题请
开发同步（时钟）2位，模16二进制编码十进制（BCD）递增计数器的行为VHDL模型。
计数器应从0到15计数，然后再从0继续。
计数器应具有有效的高CLR信号，以便随时将其内容重置为0。
计数器的状态应显示在Nexys 2板的7段显示模块上。
CLK和CLR信号都应分别映射到按钮。
注意：当使用来自布什按钮的信号CLOCK为电路计时时，必须添加语句NET“CLOCK”CLOCK_DEDICATED_ROUTE = FALSE;
到您的.ucf文件。
您应该使用FPGA，7段显示器和Nexys 2板上的按钮来实现此计数器.a）分别为您的设计提供.vhd和.ucf文件的硬拷贝.b）映射您的电路
通过运行实施步骤，到位于FPGADevelopment Board上的Xilinx FPGA芯片。
在此之前，将UserConstraints（.ucf）文件添加到项目中，以便为您的设计进行正确的引脚分配。
Nexys 2 Board的Master .ucf文件可通过ClassWeb页面获得。
但是，您需要编辑它以仅保留您的.vhd文件中定义的那些信号。
仅转入设备利用率并分别使用Pad Report.Email的引脚分配部分：mass1311@yahoo.com
您的教授已被告知您试图作弊。
预计本学期成绩不及格。
----------------------------是的，我这样做是为了谋生。



以下为原文

zgd2449 wrote:
If any one can help me to solve this problem please 
Develop a behavioral VHDL model of a synchronous (clocked) 2-digit, modulo-16 binary-coded-decimal (BCD) up counter. The counter should count from 0 up to 15 and then continue from 0 again. The counter should have an active high CLR signal to reset its contents to 0 at any time. The counter's state should be displayed on the 7-segment display module of the Nexys 2 Board. Both the CLK and the CLR signals should be mapped to pushbuttons, respectively. Note: when using signal CLOCK from a bush button for clocking your circuit you must add the statement NET "CLOCK" CLOCK_DEDICATED_ROUTE = FALSE; to your .ucf file. You should implement this counter using the FPGA, the 7-segment display and push-buttons on your Nexys 2 Board.
a) Turn in a hard copy of the .vhd and .ucf files for your design, respectively. 
b) Map your circuit to the Xilinx FPGA chip that is located on your FPGA
Development Board by running the Implement step. Before doing so, add a User
Constraints (.ucf) file to your project to make proper pin assignments for your
designs. The Master .ucf file for the Nexys 2 Board is available through the Class
Web Page. However, you need to edit it to keep only those signals that are defined in
your .vhd file. Turn in only the device utilization and used pin assignments
sections, respectively, of the Pad Report. 
Email : mass1311@yahoo.com

Your professor has been notified of your attempt to cheat. 
Expect a failing grade for this semester.
----------------------------Yes, I do this for a living.

嗯......为了好玩，我在大约1小时内完成了你的作业。
也许你应该放弃课程，这只会变得更难。
--------------------------------------------------
-------------------------------我喜欢这些书：Free Range VHDL（免费），http：//www.freerangefactory
.org / site / pmwiki.php / Main / BooksVHDL for Logic Synthesis，Andrew RushtonFPGA Prototyping by VHDL examples，Pong P Chu



以下为原文

Hmmm... For fun I did your assignment in about 1hr. Maybe you should drop the class, it's only going to get harder from here. 
---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu