怎么在PS中产生100Mhz的时钟信号在外部被PL接收

感谢您的回复
我实际上是试图通过将输出驱动到LED来检查时钟频率是否为100Mhz。
我正在使用示波器测量频率，但没有任何效果
你能告诉我实例化是否正确
signal stop_clock：std_logic：='1';
signal hold_clock_low：std_logic：='0';
signal hold_clock_high：std_logic：='0';
ODDR_inst：ODDR通用映射（DDR_CLK_EDGE =>“OPPOSITE_EDGE”， - “OPPOSITE_EDGE”或“SAME_EDGE”INIT =>'0'， -  Q端口的初始值（'1'或'0'）SRTYPE =>“SYNC
“） - 复位类型（”ASYNC“或”SYNC“）端口映射（Q => FX3_CLK， -  1位DDR输出C => Clk_OUT_pin， -  1位时钟输入CE => stop_clock， -  1
位时钟使能输入D1 =>'1'， -  1位数据输入（上升沿）D2 =>'0'， -  1位数据输入（下降沿）R => hold_clock_low， -  1-
位复位输入S => hold_clock_high  -  1位置位输入
在原帖中查看解决方案



以下为原文

Thanks for your reply
 
I actually am trying to check if the clock freq is 100Mhz by driving the output to an LED.
I am measuring the freq using an oscilloscope but nothing worked
 CAN you tell if my instantiation is correct
 
signal stop_clock : std_logic := '1';
  signal hold_clock_low : std_logic := '0';
  signal hold_clock_high : std_logic := '0';
 
 
ODDR_inst : ODDR
       generic map(
          DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
          INIT => '0',   -- Initial value for Q port ('1' or '0')
          SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
       port map (
          Q => FX3_CLK,   -- 1-bit DDR output
          C => Clk_OUT_pin,    -- 1-bit clock input
          CE => stop_clock,  -- 1-bit clock enable input
          D1 => '1',  -- 1-bit data input (positive edge)
          D2 => '0',  -- 1-bit data input (negative edge)
          R => hold_clock_low,    -- 1-bit reset input
          S => hold_clock_high     -- 1-bit set input
 
View solution in original post

这意味着两件事之一，你没有正确实现设计，或者你没有探测正确的输出引脚。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

This means one of two things, you did not implement the design correctly or you did not probe the correct output pin.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

感谢您的回复
我实际上是试图通过将输出驱动到LED来检查时钟频率是否为100Mhz。
我正在使用示波器测量频率，但没有任何效果
你能告诉我实例化是否正确
signal stop_clock：std_logic：='1';
signal hold_clock_low：std_logic：='0';
signal hold_clock_high：std_logic：='0';
ODDR_inst：ODDR通用映射（DDR_CLK_EDGE =>“OPPOSITE_EDGE”， - “OPPOSITE_EDGE”或“SAME_EDGE”INIT =>'0'， -  Q端口的初始值（'1'或'0'）SRTYPE =>“SYNC
“） - 复位类型（”ASYNC“或”SYNC“）端口映射（Q => FX3_CLK， -  1位DDR输出C => Clk_OUT_pin， -  1位时钟输入CE => stop_clock， -  1
位时钟使能输入D1 =>'1'， -  1位数据输入（上升沿）D2 =>'0'， -  1位数据输入（下降沿）R => hold_clock_low， -  1-
位复位输入S => hold_clock_high  -  1位置位输入



以下为原文

Thanks for your reply
 
I actually am trying to check if the clock freq is 100Mhz by driving the output to an LED.
I am measuring the freq using an oscilloscope but nothing worked
 CAN you tell if my instantiation is correct
 
signal stop_clock : std_logic := '1';
  signal hold_clock_low : std_logic := '0';
  signal hold_clock_high : std_logic := '0';
 
 
ODDR_inst : ODDR
       generic map(
          DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
          INIT => '0',   -- Initial value for Q port ('1' or '0')
          SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
       port map (
          Q => FX3_CLK,   -- 1-bit DDR output
          C => Clk_OUT_pin,    -- 1-bit clock input
          CE => stop_clock,  -- 1-bit clock enable input
          D1 => '1',  -- 1-bit data input (positive edge)
          D2 => '0',  -- 1-bit data input (negative edge)
          R => hold_clock_low,    -- 1-bit reset input
          S => hold_clock_high     -- 1-bit set input
 

你能告诉我设计的哪一部分可能是错的



以下为原文

Can you tell me which part of the design may be wrong

根据您的信号名称，这只是一个疯狂的猜测，但在我看来，您希望使用Clk_OUT_pin将时钟驱动到外部引脚，而FX3_CLK是来自PS的时钟？
如果这是正确的，那么FX3_CLK连接到ODDR的输出，而Clk_OUT_pin连接到ODDR的输入，这似乎是向后的。
如果Clk_OUT_pin确实是你想要用作输入的东西而且FX3_CLK确实是你想要用作输出的东西，那么在约束文件中必然存在其他错误，例如不正确的LOC（或没有LOC）。
我还建议您将信号名称从“stop_clk”更改为“enable_clk”，因为它更好地匹配该信号的目的和极性。
干杯，
-Doug



以下为原文

This is just a wild guess based on your signal names, but it looks to me like you want to use Clk_OUT_pin to drive your clock out to the external pin and FX3_CLK is the clock coming from the PS?
 
If that's correct, then you have FX3_CLK connected to the output of the ODDR, and Clk_OUT_pin connected to the input of the ODDR which would seem to be backwards.  If Clk_OUT_pin really is what you want to use as input and FX3_CLK really is what you want to use as output, then there must be something else amiss such as an incorrect LOC (or no LOC) in the constraints file.
 
I would also suggest you change the signal name from "stop_clk" to "enable_clk" as it matches the purpose and polarity of that signal better.
 
Cheers,
-Doug

第一个答案：输出FX3_CLK以驱动时钟输出.Clk_OUT_pin从处理器系统中输出。我将其更改为enable_clk要做的任何其他更改？



以下为原文

1st answer : FX3_CLK is output to drive the clock out.
The Clk_OUT_pin is out from the processor system.

and I changed it as enable_clk any other changes to be done??

>你可以告诉我实例化是否正确
对于ODDR，实例化是正确的，过于复杂且名称混乱，但仍然正确。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

>  CAN you tell if my instantiation is correct
 
The instantiation is correct for the ODDR, overly complicated and with confusing names, but still correct.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

哦对不起！！！
但这些名字取自xilinx ISE misc示例......任何其他解决方案....



以下为原文

Oh sorry!!! but these names were taken from xilinx ISE misc example...

any other solutions ....

我已经完成了你正在尝试的东西，我使用ODDR从PS转发了一个100MHz的时钟，它工作正常。
由于您的ODDR实例化看起来正确，因此两个最高概率答案是：
1）您的输出信号没有到达您认为的引脚
2）您的输入信号不是时钟
我建议将一个已知的好时钟（例如常规逻辑时钟）连接到ODDR的输入并检查输出引脚。
如果您仍未在输出上看到时钟，则可能是输出引脚设置/选择导致您的问题。
如果你确实看到输出上的时钟，那么可能是你连接到PS的时钟信号就是问题所在。
干杯，
-Doug



以下为原文

I have done exactly what you're attempting, I forwarded a 100MHz clock from the PS out a pin using ODDR, and it worked fine.  Since your ODDR instantiation looks correct, the two highest probability answers are:
 
1) Your output signal is not getting to the pin you think it is
2) Your input signal is not a clock
 
I would suggest hooking a known good clock such as your regular logic clock to the input of the ODDR and checking your output pin.  If you still don't see the clock on the output, it's probably the output pin setup/selection that's causing your problem.  If you do see the clock on the output, then it's probably your connection to the clock signal from the PS that's the problem.
 
Cheers,
-Doug

Hii Doug，来自PS的我的时钟很好我正在同时检查它。你能给我你的顶级文件可能是我在那里犯了一些错误.regardsRaj



以下为原文

Hii Doug,
My clock from the PS is fine I am checking it simultaneously.
Can you give me your top file may be I made some mistakes there.

regards
Raj