如何导入鹰电路设计

我如何编辑自己的帖子？
无论如何：这是一个.sch格式的例子，我的设计保存在......



以下为原文

how do I edit my own posts here?
 
anyway: here is an example of the .sch format my design is saved in...

目前尚不清楚你要做什么。
这是一个板级原理图，还是一个进入FPGA的逻辑原理图。
Xilinx工具链仅适用于FPGA内部的逻辑，而不适用于板级设计。
一些原理图编辑器可以以EDIF或结构VHDL格式导出网表。
Xilinx后端工具可以使用其中任何一个来编译设计。
无法将图形化原理图直接导入Xilinx原理图。
-  Gabor
PS新用户可能无法在某个介绍期间编辑自己的帖子。
添加此项是为了减少此论坛上的垃圾邮件帖子。
在此期间，请按照您的要求继续回复您自己的帖子。
当您超过介绍期后，您应该开始在“选项”菜单中看到“编辑回复”。
-  Gabor



以下为原文

It's not clear what you're trying to do.  Is this a board-level schematic or is it a schematic of the logic that goes into the FPGA.   The Xilinx tool chain is only for the logic inside the FPGA, not the board-level design.  Some schematic editors can export a netlist in EDIF or structural VHDL format.  Either of these can be used by the Xilinx back-end tools to compile the design.  There is no way to directly import a graphical schematic into the Xilinx schematics.
 
-- Gabor
 
PS  New users may not edit their own posts for a certain introductory period.  This was added to reduce spam posts on this forum.  In the meantime go ahead and reply to your own posts as you have done.  When you have past the introductory period, you should start to see "Edit Reply" in the Options menu.
-- Gabor

嗨，
你是否想要在FPGA-Talk上发布c64模拟器？
您具有相同的用户名。
无论如何...
即使您只有数字部件的鹰图，这些名称也不会与Xilinx原理图符号名称相匹配，因此即使转换它也无济于事。
（除了这两种格式之间可能没有转换器这一事实）
所以你需要再次绘制原理图，如果它有用的话。
也许某些HDL描述会在更短的时间内提供更好的结果，具体取决于您要创建的硬件。
有一个很好的综合 
Eilert



以下为原文

Hi,
are you the same guy that wants tu build the c64 emulator as posted on FPGA-Talk?
You have the same user name.
 
Anyway...
 
Even if you have some eagle schematic with just digital parts, the names wont match the Xilinx schematic symbol names so even converting it wouldn't help. (Besides the fact that there probably is no converter between these two formats)
 
So you need to draw the schematics again, if that is useful at all.
Maybe some HDL description gives better results in less time, depending on the hardware you want to create.
 
Have a nice synthesis
  Eilert
 
 
 

“一些原理图编辑器可以导出EDIF或结构VHDL格式的网表.Xilinx后端工具可以使用其中任何一个来编译设计。”
再一次问好
哪里？
我在哪里可以导入这些网表（如果他们有正确的格式）
我自己找不到它......
thanx你的答案！
奥利弗



以下为原文

"Some schematic editors can export a netlist in EDIF or structural VHDL format.  Either of these can be used by the Xilinx back-end tools to compile the design."
 
hello again
 
where?
where can I import these netlists (in case they do have the right format)
I couldn't find it it myself...
 
 thanx for your answer !
oliver
 

e2020写道：
“一些原理图编辑器可以导出EDIF或结构VHDL格式的网表.Xilinx后端工具可以使用其中任何一个来编译设计。”
再一次问好
哪里？
我在哪里可以导入这些网表（如果他们有正确的格式）
我自己找不到它......
thanx你的答案！
奥利弗
难道EAGLE没有可以回答这个问题的支持论坛吗？
或者你不能进入1996年并使用HDL？
----------------------------是的，我这样做是为了谋生。



以下为原文

e2020 wrote:
"Some schematic editors can export a netlist in EDIF or structural VHDL format.  Either of these can be used by the Xilinx back-end tools to compile the design."
 
hello again
 
where?
where can I import these netlists (in case they do have the right format)
I couldn't find it it myself...
 
 thanx for your answer !
oliver
 

Doesn't EAGLE have a support forum which could answer that question?
Or can't you move forward to 1996 and use an HDL?
----------------------------Yes, I do this for a living.

我在哪里可以导入这些网表（如果他们有正确的格式）
尝试EDIF2NGD，命令行工具用户指南（UG628）中的附录B.
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

where can I import these netlists (in case they do have the right format)
 
Try EDIF2NGD, Appendix B in the Command Line Tools User Guide (UG628).
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
我在哪里可以导入这些网表（如果他们有正确的格式）
尝试EDIF2NGD，命令行工具用户指南（UG628）中的附录B.
- 鲍勃埃尔金德
您还可以创建一个新项目并将“EDIF”设置为顶级输入样式。
所有这一切，这假设这些原理图只包含符号
Xilinx后端工具可以理解这一点。
也就是说，他们必须在
Xilinx库（unisims，simprims等）或在您的层次结构中描述
原理图到原始水平。
你不能采用板级原理图
使用像74LS163这样的符号，并期望工具了解其工作原理。
-  Gabor
-  Gabor



以下为原文

eteam00 wrote:
where can I import these netlists (in case they do have the right format)
 
Try EDIF2NGD, Appendix B in the Command Line Tools User Guide (UG628).
 
-- Bob Elkind

You can also create a new project and set "EDIF" as the top-level entry style.
 
All that being said, this presumes that these schematics only contain symbols
that are understood by the Xilinx back-end tools.  That is, they must be in the
Xilinx libraries (unisims, simprims, etc.) or hierarchically described in your
schematic down to the primitive level.  You can't take a board level schematic
with symbols like a 74LS163 and expect the tools to understand how that works.
 
-- Gabor
-- Gabor