0到9的计数器怎么使用顺序逻辑

是什么令你感到困惑？
你应该写下你想要实现的目标，然后考虑如何编写每个阶段的代码。
例如，当清除输入为逻辑1时，计数器应在下一个上升时钟沿复位为0。
当使能输入为逻辑1时，计数器应在每个上升时钟沿递增。
这些只是一些例子。
您应该考虑您的要求并相应地应用它们。
就个人而言，我会同步完成整个事情。
问候，
霍华德
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

What is it that is confusing you?
 
You should write down what it is you are trying to achieve and then consider how to code each of those stages. For example, when the clear input is a logic 1, the counter shall be reset to 0 on the next rising clock edge. When the enable input is a logic 1, the counter shall increment on every rising clock edge.
 
These are just examples. You should consider what requirements you have and apply them accordingly.
 
Personally, I would do the whole thing synchronously.
 
Regards,
 
Howard
 
----------
"That which we must learn to do, we learn by doing." - Aristotle

参见UG616，标题为CD4CE的部分。
此功能类似于图中的功能。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

See UG616, section titled CD4CE.  This function is similar to the function in your diagram.
 
-- Bob Elkind
SIGNATURE:
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1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

模块counter_0to9（输入ena，输入clr，输入clk，输出reg [3：0] q，输出reg carry_out）;
如果（clr == 1）开始q = 4'b0000，则始终@（ena，clr）;
结束if（clr == 0＆amp;＆amp; ena == 1）开始q = 4'b0000;
结束if（ena == 1）begin q carry_out = 0;
结束if（q == 4'b1001）carry_out = 1;
结束总是@（posedge clk）开始q结束
endmodule
这是正确的吗？？？



以下为原文

module counter_0to9(
input ena,
input clr,
input clk,
output reg [3:0] q,
output reg carry_out
);

always @(ena, clr) begin
if (clr==1) begin
q=4'b0000; end

if (clr==0 && ena==1) begin
q=4'b0000; end


if (ena==1) begin
q<=4'b0001;
carry_out=0; end

if (q==4'b1001)
carry_out=1;

end

always @(posedge clk) begin
q<=ena;



end
endmodule
 
is this right???

这是测试向量10_0000011_0000001_0000101_0001001_0001101_0010001_0010101_0011001_0011101_0100001_1100100_0100101_0000001_0000101_0001001_0001101_0010000_0010001_0010101_0011001_0011101_0100001_1100101_0000001_0000111_00000



以下为原文

here is the test vectors

10_00000
11_00000
01_00001
01_00010
01_00011
01_00100
01_00101
01_00110
01_00111
01_01000
01_11001
00_01001
01_00000
01_00001
01_00010
01_00011
01_00100
00_00100
01_00101
01_00110
01_00111
01_01000
01_11001
01_00000
01_00001
11_00000

总是@（posedge clk）q
这是正确的吗？？？
不，你是在为期16周的Verilog学习课程的第2周。
或者是为期5天的课程的第1天。
为什么使用两个单独的进程而不是单个进程？
这种风格有什么好处吗？
了解阻止和非阻塞分配之间的区别。
不允许在多个（不同）进程中为寄存器或变量赋值。
每个变量或寄存器的所有赋值必须包含在一个进程中。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

always @(posedge clk)
q<=ena;
 
is this right???
 
No.  You are in week 2 of a 16-week Verilog study course.  Or day 1 of a 5-day course.
 

• Why are you using two separate processes instead of a single process?  Is there some benefit to this style?
  

• Understand the difference between blocking and non-blocking assignments.
  

• It is not permitted to assign values to a register or variable in multiple (different) processes.  All assignments for each variable or register must be contained in a single process.
  

 
-- Bob Elkind
SIGNATURE:
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Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我使用两个总是块，因为这是我的老师想要的



以下为原文

Im using two always blocks because that's how my teacher wanted

我使用两个总是块，因为这是我的老师想要的
问老师“为什么”。
通常的做法是使用单个时钟进程。
如果他或她倾向于邀请您的老师在这些论坛中讨论这个问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Im using two always blocks because that's how my teacher wanted
 
Ask your teacher "why".
 
Common practice is to use a single, clocked process.  Invite your teacher to discuss this in these forums if he or she is inclined.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

这项任务的另一部分被称为除以100计数器......你对此有何了解？



以下为原文

There is another part of this assignment its called divide by 100 counter...do u know anything about that?

这项任务的另一部分被称为除以100计数器......你对此有何了解？
是。
这是今天的学习练习吗？
为了额外的功劳，为什么不在两个进程（对于您的教师）和单个进程中实现它，然后询问您的教师为什么一个实现应优先于其他实现。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

There is another part of this assignment its called divide by 100 counter...do u know anything about that?
 
Yes.  Is this today's learning exercise?  For extra credit, why don't you implement this is in both two processes (for your instructor) and a single process, and then ask your instructor why one implementation should be preferred over the other implementation.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

你似乎在这个项目上失去了绝望（任务？），我很惊讶鲍勃
还没有建议你和老师一起一对一的时间
助教/导师。
你不太可能知道你需要知道的东西
在这个论坛上。
包括鲍勃和我在内的很多人都可以做到这一点
在睡眠中分配，但这并不能真正帮助你学习如何描述
Verilog中的硬件。
但是既然你发布了一些代码，我会添加一些批评：
总是@（ena，clr）开始
在这里你已经陷入困境了。
对于组合过程，您需要
在灵敏度列表中包含所有右侧信号。
Verilog 2001有一个
简单的解决方案，以确保您没有错过任何：
总是@ *开始
在你的情况下，你在灵敏度列表中错过了“q”。
if（clr == 1）开始
忘记了这一点并没有真正做到你想要的那一刻，它表明了这一点
您正在尝试编写Verilog代码，就好像它是VHDL一样。
两者之间没有区别
Verilog中的一位reg，wire或“boolean”。
我发现写起来更清楚：
if（clr）开始
现在问题的关键。
您正在为顺序进行分配
组合过程中的变量“q”。
这是错的。
唯一的任务
“q”应该在计时过程中。
如果你已经走得太远，试图合成
这段代码，您还会发现在分配变量时出错
不止一个过程。
如果你坚持使用这个计数器的两个进程，你需要
另一个变量代表你将在下一个分配“q”的值
时钟边缘。
您的模块没有定义内部变量。
很简单
如果没有一些，就不能使用双进程状态机
额外的中间变量。
基本的双进程状态机看起来像（伪代码）
reg [3：0] q_next;
总是@ * 
q_next = q的一些函数和模块输入;
永远@（posedge clk） 
q
如果clear输入是异步的，则第二部分看起来像：
永远@（posedge clk，posedge clr） 
if（clr）q 
否则q
但是说真的，从老师那里得到一些帮助。
这就是他付出的代价。
-  Gabor
-  Gabor



以下为原文

You seem to be hopelessly lost on this project (assignment?) and I'm surprised that Bob
hasn't already suggested that you get some one-on-one time with your teacher or a
teaching assistant / tutor.  It's not likely that you will be able to learn what you need to know
on this forum.  There are many people including Bob and myself who could do this
assignment in their sleep, but that doesn't really help you learn how to describe
hardware in Verilog.
 
But since you went so far as to post some code, I'll add a few critiques:
 
always @(ena, clr) begin
 
Here you're already getting in trouble.  For a combinatorial process you need to
have all of the right-hand-side signals in the sensitivity list.  Verilog 2001 has a
simple solution to make sure you didn't miss any:
 
always @* begin
 
In your case you missed "q" in the sensitivity list.
 
if (clr==1) begin
 
Forgetting that this doesn't really do what you want for the moment, it shows that
you are trying to write Verilog code as if it were VHDL.  There is no difference between
a one-bit reg, wire, or "boolean" in Verilog.  I find it much clearer to just write:
 
if (clr) begin
 
Now to the meat of the problem.  You are making assignments to the sequential
variable "q" in a combinatorial process.  This is wrong.  The only assignments to
"q" should be in the clocked process.  If you had gone so far as to try to synthesize
this code, you would also find that you get an error for assigning the variable in
more than one process.
 
If you insist on using two processes for this counter, you need to have
another variable to represent the value you will assign "q" on the next
clock edge.  Your module has no internal variables defined.  Quite simply
put you cannot use a two-process state machine without having some
additional intermediate variables.
 
The basic two-process state machine looks like (pseudo code)
 
reg [3:0]  q_next;
always @*
  q_next = some function of q and the module inputs;
 
always @ (posedge clk)
  q <= q_next;
 
If the clear input is asynchronous the second part looks like:
 
always @ (posedge clk, posedge clr)
  if (clr) q <= 0;
  else q <= q_next;
 
But seriously, get some help from your teacher.  That's what he's paid for.
 
-- Gabor
-- Gabor

的Gabor ...
但是说真的，从老师那里得到一些帮助。
这就是他付出的代价。
我们都熟悉正统的双过程状态机。
两州的柜台有点意外。
我怀疑这是Verilog编码世界的新时尚。
我想我们中的任何一个都有兴趣参与讨论教授这种编码风格的讲师。
还有（至少）一个额外的问题，这表明Sandee是最早引入Verilog的。
该练习表面上是一个计数器，但是没有计数逻辑可以找到，无论是优雅的语法还是粗俗的语法。
除了学习Verilog（或VHDL）之外，学习“逻辑和逻辑设计”和“硬件设计”也很重要。
Verilog是一个设计工具。
学习工具与学习设计不同。
一步一步，耐心......
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

Gabor...
 
But seriously, get some help from your teacher.  That's what he's paid for.
 
We are all familiar with the two-process state machine orthodoxy.
Two-state counters are a bit of surprise.  I doubt that this is a new fashion in the world of Verilog coding.
 
I think either of us would be interested in engaging in discussion the instructor who is teaching this coding style.
 
There is (at least) one additional problem which suggests that Sandee is in the very earliest introduction to Verilog.  The exercise is ostensibly a counter, and yet there is no counting logic to be found, either in elegant syntax or crude syntax.  In addition to learning Verilog (or VHDL), it is also important to learn "logic and logical design" and "hardware design".  Verilog is a tool for design.  Learning the tool is not the same as learning to design.
 
One step at a time, with patience...
 
-- Bob Elkind
SIGNATURE:
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Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我不确定为什么你对双进程计数器感到惊讶。
计数器是状态机。
您引用的库指南页面有一个清晰绘制的状态转换图
像任何其他状态机一样。
计数器被推断为一种特殊的机器
（为了使用进位逻辑）实际上并没有改变它可以在一个中描述的事实
或两个过程。
当一个人完成工作并且这样做时，我不主张使用两个过程
更清楚，但一般来说形式的任何等式：
总是@（posedge clk）foo
也可以写成：
总是@ * grob = baz + bar;
总是@（posedge clk）foo
目前还不清楚为什么这么多入门级逻辑设计课程选择这种写作方法
硬件描述。
巴斯曼似乎认为它与早期的合成器有关
这需要一个两部分的过程来正确推断状态机。
HDL不在身边
当我在大学学习逻辑设计时。
我学会了如何使用卡诺图来翻译
真相表进入大门。
现在使用FPGA架构，您可以使用计算机进行翻译
进入真值表。
入门级设计课程可能需要您
将“门”与触发器分开显示。
无论如何，我同意这一点
在数字设计和布尔代数之前拥有扎实的背景非常重要
涉足硬件描述语言。
-  Gabor
-  Gabor



以下为原文

I'm not sure why you're surprised about two-process counters.  A counter is a state machine.
The library guide page you referenced has a clearly drawn state transition diagram that looks
like any other state machine.  The fact that counters are inferred as a special kind of machine
(in order to use the carry logic) really doesn't change the fact that it can be described in one
or two processes.  I don't advocate using two processes when one will do the job and do it
more clearly, but in general any equation of the form:
 
always @ (posedge clk) foo <= baz + bar;
 
can also be written:
 
always @* grob = baz + bar;
 
always @ (posedge clk) foo <= grob;
 
It's unclear why so many entry level logic design courses choose this method of writing
hardware descriptions.  Bassman seems to think it has to do with early synthesizers
that needed a two-part process to properly infer state machines.  HDL's were not around
when I studied logic design in college.  I learned how to use Karnaugh maps to translate
truth tables into gates.  Now with FPGA architectures you use a computer to translate
gates into truth tables.  It's possible that the entry level design course wants you to
visualize the "gates" separately from the flip-flops.  In any case I would agree that it
is important to have a solid background in digital design and boolean algebra before
wading into hardware description languages.
 
-- Gabor
-- Gabor

“目前还不清楚为什么如此多的入门级逻辑设计课程选择这种编写硬件描述的方法。”也许这是为了清楚地将保持计数值的寄存器与控制它的逻辑分开。
如果您从SSI门和触发器或使用原理图捕获滚动您自己的设计，这是相当明智的。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"It's unclear why so many entry level logic design courses choose this method of writing hardware descriptions."

Perhaps it's to clearly separate the registers that hold the count value from the logic that controls it. If you are rolling your own design from SSI gates and flip-flops, or using schematic capture, this is fairly sensible.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

sandeepdarar写道：我使用两个总是块，因为这是我的老师想要的
你的老师很傻。
----------------------------是的，我这样做是为了谋生。



以下为原文

sandeepdarar wrote:
Im using two always blocks because that's how my teacher wanted

Your teacher is a fool.
----------------------------Yes, I do this for a living.

gszakacs写道：
目前还不清楚为什么这么多入门级逻辑设计课程选择这种写作方法
硬件描述。
巴斯曼似乎认为它与早期的合成器有关
这需要一个两部分的过程来正确推断状态机。
我学习了状态机和K-maps作为本科生，当时没有HDL这样的东西。
我对HDL的第一次介绍是PALASM（PAL的汇编语言），CUPL（同上）和Altera的AHDL。
但我确实记得在非常早期的Xilinx Alliance / Foundation中使用带有Synopsis FPGA Express的VHDL，并且文档非常清楚需要双进程状态机，因为该工具根本无法识别未经过特定编码的状态机
他们的要求。
我怀疑课程材料和山丘一样古老，需要升级。
我的第二个怀疑是，单进程状态机的流水线特性使新手感到困惑 - “我分配到状态S_X，但波形显示显示事情发生了变化！”
课程选择完全绕过它，而不是解决这种混乱。
----------------------------是的，我这样做是为了谋生。



以下为原文

gszakacs wrote:
 
It's unclear why so many entry level logic design courses choose this method of writing
hardware descriptions.  Bassman seems to think it has to do with early synthesizers
that needed a two-part process to properly infer state machines.

I learned state machines and K-maps as an undergrad, and back then there was no such thing as an HDL. My first introduction to HDLs was PALASM (assembly language for PALs), CUPL (ditto) and then Altera's AHDL. 
 
But I do remember using VHDL with Synopsis FPGA Express with very early Xilinx Alliance/Foundation, and the docs were quite clear on the need for the two-process state machine, as the tool simply wouldn't recognize a state machine not coded specifically to their requirements.
 
My suspicion is that the course material is as old as the hills and needs an upgrade. My second suspicion is that the pipelined nature of a one-process state machine confuses the newbies -- "I assigned to state S_X but the waveform display shows things changing late!" Rather than address that confusion, the courses opt to bypass it entirely.
----------------------------Yes, I do this for a living.

我第一次介绍可编程逻辑也是通过PALASM。
有趣的是
PALASM如果你试图将一个方程分成它的组合和顺序
您在硬件​​中生成额外节点（读取额外宏单元）的组件。
因此，将两进程方法用于状态逻辑绝对没有意义。
在那些日子里（PAL16L8,16R8等），每个宏单元都非常昂贵
我的大多数状态机都是为了使状态变量成立而设计的
尽可能多的期望产出。
你很快习惯了思考
关于在下一个时钟周期中根据条件需要发生什么
时钟周期。
也许这就是为什么我从来没有考虑过这两个过程的FSM
作为一种选择。
大多数情况下，尽管我喜欢尽可能多地看到逻辑
一个屏幕的文字，所以任何增加行数的事都困扰着我。
这包括双进程FSM以及空白行的过度使用
适当的缩进将实现相同的可读性。
-  Gabor
-  Gabor



以下为原文

My first introduction into programmable logic was also via PALASM.  Interestingly in
PALASM if you try to separate an equation into its combinatorial and sequential
components you generate an extra node (read extra macrocell) in the hardware.
So it definitely made no sense to use the two-process approach to state logic.
In those days (PAL16L8, 16R8, etc.) each macrocell was cery expensive and
most of my state machines were designed such that the state variable consisted
of the desired outputs as much as feasible.  You very quickly get used to thinking
about what needs to happen in the next clock cycle based on conditions at this
clock cycle.  Maybe that's why I never even considered the two-process FSM
as an option.  Mostly, though I like to see as much of the logic as I can in
one screenful of text, so anything that increases the line count bothers me.
This includes two-process FSM's as well as the over-use of blank lines when
proper indenting would achieve the same readability.
 
-- Gabor
-- Gabor

muzaffer写道：
通过将寄存器和组合逻辑放在单独的进程中来完成两个进程设计。
您需要弄清楚您的加法器应该做什么以及如何将其划分为寄存器并根据当前寄存器输出的值计算下一个值。
这是一些帮助：
reg [3：0] q;
//这是存储输出的寄存器
reg [3：0] q_next;
//这些变量将用于计算当前寄存器值的下一个值
所以当时钟事件发生时，q应该只是复制计算出的下一个值，即
q
但为什么？
这两个过程的习惯用法过于复杂，通常不是必需的。
----------------------------是的，我这样做是为了谋生。



以下为原文

muzaffer wrote:
Two process design is done by putting registers and combinational logic in separate processes. You need to figure out what your adder is supposed to do and how to partition it into registers and calculation of the next value based on the value of the current register outputs. Here is some help:
 
reg [3:0] q; // this are the registers which will store the output
 
reg [3:0] q_next; // these are the variables which will be used to calculate the next value from current register values
 
so when clock event happens q should just make a copy of the calculated next value ie
q <= q_next;
 
q_next depends on the current value so for a very basic incrementer you need to say:
q_next = q + 1;
 
You need to make sure q gets evaluated only one a clock edge and q_next is a blob of logic which evaluates its input whenever q changes.
 
HTH.

But why? The two-process idiom is overcomplicated and not generally necessary.
----------------------------Yes, I do this for a living.

它可能没有必要但足够了;-)
这些天它可能只用于恐龙，他们习惯于使用原理图设计数字逻辑，他们手动丢弃寄存器和门，他们想要一个类似于它的文本输入系统。
或者由同样写的书仍然显示流动。
当然，单一过程逻辑也提供了更好的编码风格，更易于理解，并为更高的抽象提供了更多的机会，但谁需要所有......
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

It may not be necessary but it is sufficient ;-)
 
These days it's probably used only by dinosaurs who are used to designing digital logic with schematics where they drop registers and gates manually and they would want to a text entry system which resembles that. Or books written by the same which still show that flow.
 
Of course single process logic also affords better coding style, easier to understand and gives more opportunity for higher abstraction but who needs all that ...
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