PIC24HJ64GP506A WDT在保持GPIO的同时复位

嘿，大家好！我使用API24HJ64 GP506A进行一个项目，并有一个架构问题。该PIC用于通过串行连接启用/禁用各种外部组件（通过GPIO）。在WDT超时/重置（例如，由于软件错误）的情况下，理想的是，在检查RCON和检测WDT重置之后，我希望保持TrIS/LAT配置。我知道在任何重置事件中，所有TRIS寄存器都被重置为输入。这可能会导致各种下游组件的电源可能出现错误状态。我的第一个解决方案是追踪导致WDT重置的错误并防止重置再次发生。不管怎样，我仍然希望WDT保护能够防止潜在的锁定。我曾经想到的一种解决方案是使用三态缓冲器，其中缓冲器输出值在主动驱动时才改变。这将保持输出值，直到PIC完全重新初始化。另一个建议的解决方案是使用连接到高优先级中断的外部看门狗电路。在这个ISR中，我可以重置主循环的PC到主程序的开头（）。我不确定到底该怎么做，或者是否有可能。有没有其他人遇到过这种情况，或者有什么想法可以帮助？谢谢，伊北



      以下为原文

    Hey everyone!

I am using a PIC24HJ64GP506A for a project and have an architectural problem. This PIC is used to enable/disable various external components (via GPIO) over a serial connection. In the event of a WDT timeout/reset (due to a software bug for example), ideally I would want to maintain the TRIS/LAT configuration after inspecting RCON and detecting a WDT reset. I know that during any reset event, all TRIS registers are reset to inputs. This can cause blips in the power to the various downstream components which may leave them in a bad state.

My first solution will be to track down the bug that is causing the WDT reset and prevent the reset from ever happening again. Regardless of this, I still want the WDT protection against potential lockups.

One solution I've thought of is using a tri-state buffer of sorts, where the buffer output value is only changed when it is actively driven. This would maintain the output value until the PIC has fully reinitialized.

Another proposed solution is to use an external watchdog circuit connected to a high priority interrupt. In this ISR, I could reset the PC of the main loop to the beginning of main(). I am not sure exactly how I would do this or if it is possible at all.

Has anyone else come across this scenario or have any ideas that could help?

Thanks,
Nate