Spartan 6 Camera Link接收器改进设计技巧

我不确定Spartan 6是否允许这样做，但我想你可以拿走时钟
从标准IOB引脚输入并使用CLOCK_DEDICATED_ROUTE约束
允许它连接到PLL。
我不认为SERDES会有所帮助。
我通常只使用3.5x时钟的DDR输入触发器
来自PLL ..标准ISERDES设计的最大问题在于你
需要找到时间这个词，当你没有训练模式时，这会变得很难
从源头（我想你的情况下是一台相机？）。
我所做的是运行所有输入
包括通过IDDR寄存器的时钟。
“反序列化”时钟可以轻松实现
发现单词边界。
棘手的部分是将时钟输入连接到PLL
和IDDR注册。
我没有在S6中尝试过这个，但是在V5中我使用了IBUFDS_DIFF_OUT
并将其非反相输出路由至PLL，并将其反相输出路由至IDDR触发器。
你必须使用PLL相位来找到最佳采样点，但是
对于单个输入频率来说这不应该太难（比试图处理它更容易）
完整的20-85 MHz Camera Link系列）。
非专用时钟路由会影响
理想的阶段。
你应该仔细检查后期P＆amp; R静态时序报告“datasheet”
确保输入设置和保持时间在最小 - 最大值上看起来足够的部分
报道范围。
-  Gabor
-  Gabor



以下为原文

I'm not sure if this is allowed in Spartan 6, but I would imagine you could take the clock
input from the standard IOB pins and use the CLOCK_DEDICATED_ROUTE constraint
to allow it to connect to a PLL.
 
I don't think SERDES will help.  I normally just use DDR input flops using a 3.5x clock
from the PLL..  The biggest problem with the standard ISERDES design is that you
need to find the word timing, and this gets tough when you don't have a training pattern
from the source (I suppose a camera in your case?).  What I do is run all of the inputs
including the clock through IDDR registers.  "deserializing" the clock allows you to easily
spot the word boundaries.  The tricky part is connecting the clock input to both a PLL
and the IDDR register.  I haven't tried this in S6, but in V5 I used an IBUFDS_DIFF_OUT
and routed its non-inverting output to the PLL and its inverting output to the IDDR flops.
 
 You have to play with the PLL phase to find the best sampling point, but
that shouldn't be too hard for a single input frequency (much easier than trying to handle the
complete 20-85 MHz Camera Link range).  The non-dedicated clock routing will affect the
ideal phase.  You should carefully check the post P&R static timing report "datasheet"
section to make sure that the input setup and hold times look adequate over the min - max
reported range.
 
-- Gabor
-- Gabor

这是对Gabor的帖子的回复，而不是Patrick的回复，因为Gabor提出了很多有趣的问题。
注意：Gabor在这些论坛（包括我自己）中被其他人普遍认可为CameraLink界面和相机到显示器设计架构的知识权威。
我不确定Spartan 6中是否允许这样做，但我想你可以从标准IOB引脚获取时钟输入并使用CLOCK_DEDICATED_ROUTE约束来允许它连接到PLL。
这在Spartan-6中是允许的（UG382特别指出PLL.CLKIN可以来自IBUF输入缓冲器），如果帕特里克尚未做到这一点，我会感到惊讶。
我不认为SERDES会有所帮助。
为什么不？
它可以完成IDDR2可以做的所有事情，还有更多。
最大的优点是IDDR2的输出比特率可以不低于采样率的一半，而ISERDES2的输出速率可以是（更易于管理的）字（像素）速率（如果大于8：1，则是字速率的2倍）
需要反序列化比率）。
我通常只使用来自PLL的3.5x时钟来使用DDR输入触发器。
如果您能说服自己ISERDES2很有用，您可能很容易（或更容易）从PLL生成14x时钟并以1：7比率SDR模式运行ISERDES2模块。
ISERDES2输出是7位字，是字（像素？）速率的2倍。
标准ISERDES设计的最大问题是你需要找到时间这个词，当你没有来自源头的训练模式时这会变得很难（我想你的情况下是一台摄像机？）。
这是应该用FRAME时钟输入解决的问题。
您必须使用PLL相位来寻找最佳采样点，但对于单个输入频率来说这不应该太难（比尝试处理完整的20-85 MHz Camera Link范围容易得多）。
这是用IDELAY2块的动态DIFF_PHASE_DETECTOR操作模式解决的问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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以下为原文

This is a reply to Gabor's post, rather than Patrick's, because many interesting questions are raised by Gabor.
Note: Gabor is generally acknowledged by others in these forums (myself included) as a knowledgeable authority on CameraLink interfaces and camera-to-display design architecture.
 
I'm not sure if this is allowed in Spartan 6, but I would imagine you could take the clock input from the standard IOB pins and use the CLOCK_DEDICATED_ROUTE constraint to allow it to connect to a PLL.
 
This is permitted in Spartan-6 (UG382 specifically states that PLL.CLKIN can be sourced from an IBUF input buffer), and I would be surprised if Patrick is not already doing exactly this.
 
 
I don't think SERDES will help.
 
Why not?  It can do everything IDDR2 can do, and considerably more.  The greatest advantage is that the output bitrate of IDDR2 can be no less than half the sampling rate, whereas ISERDES2 output rate can be the (much more manageable) word (pixel) rate (or 2x the word rate, if greater than 8:1 deserialisation ratio is needed).
 
 
I normally just use DDR input flops using a 3.5x clock from the PLL.
 
If you can convince yourself that ISERDES2 is useful, you might just as easily (or more easily) generate a 14x clock from the PLL and run the ISERDES2 blocks in 1:7 ratio SDR mode.  The ISERDES2 output would be 7-bit words at 2x the word (pixel?) rate.
 
 
The biggest problem with the standard ISERDES design is that you need to find the word timing, and this gets tough when you don't have a training pattern from the source (I suppose a camera in your case?).
 
This is the problem which is supposed to be solved with the FRAME clock input.
 
 
You have to play with the PLL phase to find the best sampling point, but that shouldn't be too hard for a single input frequency (much easier than trying to handle the complete 20-85 MHz Camera Link range).
 
This is the problem supposedly solved with the dynamic DIFF_PHASE_DETECTOR operating mode of the IDELAY2 blocks.
 
-- Bob Elkind
SIGNATURE:
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Summary:
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2. Search the forums (and search the web) for similar topics.
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标准ISERDES设计的最大问题是你需要找到时间这个词，当你没有来自源头的训练模式时这会变得很难（我想你的情况下是一台摄像机？）。
这是应该用FRAME时钟输入解决的问题。
我应该根据我使用Camera Link的经验开始我的评论
接收器已经使用Virtex 5，而不是Spartan 6.我不知道FRAME时钟
输入。
在Virtex 5上有一个“BITSLIP”输入，几乎可以保证多个输入
输入通道的框架不相同，尤其是在以高比特率运行时。
一世
Xilinx询问如何处理这个问题，他们建议使用培训模式，
当另一端是别人的相机时，这当然是不可能的
设计。
315 Mbps不在Camera Link范围的高端，只需要
用于DDR输入的157.5 MHz时钟。
这在Spartan 6中很容易实现。我发​​现了这一点
当我使用DDR输入寄存器时，整个时钟和控制更简单
ISERDES，至少对于V5。
-  Gabor
-  Gabor



以下为原文

The biggest problem with the standard ISERDES design is that you need to find the word timing, and this gets tough when you don't have a training pattern from the source (I suppose a camera in your case?).
 
This is the problem which is supposed to be solved with the FRAME clock input.
 
I should have prefaced my remarks with the fact that my experience with Camera Link
receivers has been with Virtex 5, and not Spartan 6.  I was not aware of a FRAME clock
input.  On Virtex 5 there is a "BITSLIP" input, which almost guarantees that the multiple
input channels are not framed the same, especially when running at high bit rates.  I
asked Xilinx about how to deal with this and they suggested using a training pattern,
which is of course out of the question when the other end is a camera of someone else's
design.
 
315 Mbps is not at the high end of the Camera Link range, and would only require
a 157.5 MHz clock for a DDR input.  That is easily achievable in Spartan 6.  I found that
the entire clocking and control was simpler when I used DDR input registers instead
of ISERDES, at least for V5.
 
-- Gabor
-- Gabor

Gabor写道：我不知道FRAME时钟输入。
来自Patrick的原始帖子：我支持现有的设计，其中有一个摄像机链接接收器（3个LVDS数据线和1个LVDS帧时钟）。
显然帕特里克幸运的是FRAME输入......
Spartan-6 ISERDES2模块也具有BITSLIP功能（现在没关系到它的文档记录很差！），ISERDES2模块确实存在上电时任意（随机）字帧设置的问题。
该问题的对策是断言ISERDES2块的RESET输入，这迫使所有ISERDES2块相对于输出字对齐处于一致状态。
如果您打算使用单个定时参考（在这种情况下为FRAME输入）将所有ISERDES2模块控制为一个组 - 将单个BITSLIP信号应用于所有输入数据 - 使用RST重置
输入是必不可少的
不幸的是，ISERDES2块描述的这个方面在描述之外是无用的。
以下是UG381表3-1的摘录，其中描述了ISERDES2信号端口和功能：
端口名称类型描述
RST输入仅限异步复位。
如何清楚简洁地描述复位功能？
（短暂模式暂时启用）。
我对Virtex-5或Virtex-6 ISERDES块的了解不足以表明RESET具有类似的用途和功能。
但是，似乎ISERDES输出字框架的不确定状态大大降低了BITSLIP功能的实用性。
除非Gabor确信他首先得到的答案具有权威性，否则这值得第二意见 - 如果有必要，可以提升给设计小组。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Gabor wrote:  I was not aware of a FRAME clock input.
 
From Patrick's original post:  I am supporting an existing design where a camera link receiver (3 LVDS data lines and 1 LVDS frame clock).
 
Apparently Patrick lucked out with a FRAME input...
 
Spartan-6 ISERDES2 blocks also have a BITSLIP capability (never mind for the moment that it is poorly documented!), and the ISERDES2 blocks indeed have the problem of arbitrary (random) word framing settings at power-on.  The countermeasure for this problem is to assert the RESET input to the ISERDES2 blocks, and this forces all of the ISERDES2 blocks to a consistent state with respect to output word alignment.
 
If you are going to use a single timing reference (the FRAME input, in this case) to control all of the ISERDES2 blocks as a single group -- applying a single BITSLIP signal to all of the input data -- use of the RST reset input is essential.
 
Unfortunately, this aspect of ISERDES2 block description is useless beyond description.  Here is the excerpt from UG381 Table 3-1, where the ISERDES2 signal ports and functions are described:
 
Port name   Type    Description
RST         Input   Asynchronous reset only.
 
How is that for a clear and concise description of the reset function? (facetious mode briefly enabled).
 
I do not know enough about Virtex-5 or Virtex-6 ISERDES blocks to suggest that RESET has a similar purpose and function.  It seems, however, that an indeterminate state for the ISERDES output word framing diminishes the usefulness of the BITSLIP function considerably.  Unless Gabor is confident that the answer he first received is authoritative, this is worth a second opinion -- elevated, if necessary, to the design group.
 
-- Bob Elkind
SIGNATURE:
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Summary:
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2. Search the forums (and search the web) for similar topics.
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
Gabor写道：我不知道FRAME时钟输入。
来自Patrick的原始帖子：我支持现有的设计，其中有一个摄像机链接接收器（3个LVDS数据线和1个LVDS帧时钟）。
显然帕特里克幸运的是FRAME输入......
他所谓的“LVDS帧时钟”实际上是像素（并行）速率的时钟。
它最有趣的特点是它具有4：3的占空比（四位高，三位低）。
还有四个序列化数据对，而不是三个;
我认为这只是一个错字。
Camera Link采用28位并行字并对这些位进行混洗，然后将所有位发送到四个数据对，每个数据对都进行7：1序列化。
Gabor是对的;
你不能使用bitlip功能，因为Camera Link规范不需要（甚至建议）相机发送训练模式。
但秘密在于第五对的Camera Link时钟;
占空比指示数据线上特定输入位（0到27）的时间。
如果您查看National Semiconductor DS90CR287和'288器件（两者的相同数据手册）的数据表，您将看到一个漂亮的时序图，可以清楚地了解发生了什么。
因此，我们的想法是输入时钟可以驱动PLL或DCM为IDDR生成3.5X时钟，并且还可以作为成帧时钟，因为它处于并行速率。
注意：我已经在FPGA中完成了相机（发送）端;
我从来没有做过接收器，因为虽然帧抓取器在电子方面相当简单，但你必须处理主机驱动程序和软件，这是最好的避免。
----------------------------是的，我这样做是为了谋生。



以下为原文

eteam00 wrote:
Gabor wrote:  I was not aware of a FRAME clock input.
 
From Patrick's original post:  I am supporting an existing design where a camera link receiver (3 LVDS data lines and 1 LVDS frame clock).
 
Apparently Patrick lucked out with a FRAME input...

What he calls the "LVDS frame clock" is actually a clock at the pixel (parallel) rate. Its most interesting feature is that it has a 4:3 duty-cycle ratio (high for four bit times, low for three). There are also four serialized data pairs, not three; I assume that's just a typo. Camera Link takes a 28-bit parallel word and shuffles the bits and sends it all down the four data pairs, each with 7:1 serialization.
 
Gabor is right; you can't use the bitslip feature because the Camera Link spec doesn't require (or even suggest) that the camera send a training pattern. But the secret is in the Camera Link clock on the fifth pair; that duty cycle indicates when specific input bits (0 to 27) are on the data wires. If you check out the data sheet for the National Semiconductor DS90CR287 and '288 parts (same data sheet for both), you'll see a nifty timing diagram that makes clear what's going on.  So the idea is that the incoming clock can drive a PLL or DCM to generate a 3.5X clock for the IDDRs and also act as a framing clock since it is at the parallel rate.
 
NB: I've done the camera (transmit) side in the FPGA; I've never done a receiver because while a frame grabber is fairly straightforward electronically, you've got to deal with host drivers and software, and that's a headache best avoided.
----------------------------Yes, I do this for a living.

Gabor是对的;
你不能使用bitlip功能，因为Camera Link规范不需要（甚至建议）相机发送训练模式。
但秘密在于第五对的Camera Link时钟;
占空比指示数据线上特定输入位（0到27）的时间。
如果您查看National Semiconductor DS90CR287和'288器件（两者的相同数据手册）的数据表，您将看到一个漂亮的时序图，可以清楚地了解发生了什么。
因此，我们的想法是输入时钟可以驱动PLL或DCM为IDDR生成3.5X时钟，并且还可以作为成帧时钟，因为它处于并行速率。
因此，换句话说，您可以使用BITSLIP功能。
当成帧时钟被正确成帧（7'b1100011）时，如果成帧时钟BITSLIP信号应用于所有输入，则数据输入也将被字帧化。
并且您可以生成7倍时钟（而不是3.5倍时钟）来驱动SDR模式下的Spartan-6 ISERDES2，是吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

Gabor is right; you can't use the bitslip feature because the Camera Link spec doesn't require (or even suggest) that the camera send a training pattern. But the secret is in the Camera Link clock on the fifth pair; that duty cycle indicates when specific input bits (0 to 27) are on the data wires. If you check out the data sheet for the National Semiconductor DS90CR287 and '288 parts (same data sheet for both), you'll see a nifty timing diagram that makes clear what's going on.  So the idea is that the incoming clock can drive a PLL or DCM to generate a 3.5X clock for the IDDRs and also act as a framing clock since it is at the parallel rate.
 
So, in other words, you CAN use the BITSLIP feature.  When the framing clock is properly framed (7'b1100011) then the data inputs will also be word-framed, if the framing clock BITSLIP signal is applied to all of the inputs.
 
And you can generate a 7x clock (instead of a 3.5x clock) to drive Spartan-6 ISERDES2 in SDR mode, yes?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

因此，换句话说，您可以使用BITSLIP功能。
当成帧时钟被正确成帧（7'b1100011）时，如果成帧时钟BITSLIP信号应用于所有输入，则数据输入也将被字帧化。
我对BITSLIP的问题是同步多个通道以获得相同的滑动。
事实并非如此
从数据表中可以看出BITSLIP将被重置。
再加上异步复位输入和
一个非常高速的时钟，我不愿意冒险。
基本上你说你可以重置所有
ISERDES（复位的释放最好与位时钟 -  OUCH同步）然后使用
其中一个ISERDES（连接到时钟输入，也连接到PLL）以找到正确的
如有必要，单词框架和发行位将滑动到所有5个ISERDES。
如果由于某种原因之一
5 ISERDES与其他4个失去了步伐，你怎么能发现这个？
我的设计改为使用DDR输入触发器，然后只加载一组56位寄存器，就像一个
环形缓冲区。
这大致基于莱迪思7：1解串器。
在他们的情况下，4倍变速箱输入
用来代替简单的DDR。
需要在DDR输入端运行的状态逻辑非常好
简单而且应该没有问题来满足S6的时间安排。
它还可以很好地运行全局
时钟资源，没有像ISERDES那样的花哨时钟缓冲区 - 这是文档的另一个地方
不是很清楚。
这一切都是针对V5的，而不是我的情况下的S6。
也许文档有
从那时起变得更好。
-  Gabor
-  Gabor



以下为原文

So, in other words, you CAN use the BITSLIP feature.  When the framing clock is properly framed (7'b1100011) then the data inputs will also be word-framed, if the framing clock BITSLIP signal is applied to all of the inputs.
 
The issue I had with BITSLIP was synchronizing the multiple channels to have the same slip.  It wasn't
clear from the data sheet that the BITSLIP would be reset.  Add to that the asynchronous reset input and
a very high speed clock and I wasn't willing to chance it.  Basically you're saying that you can reset all
of the ISERDES (release of reset had better be synchronous to the bit clock - OUCH) and then use
one of the ISERDES (connected to the clock input, which also goes to the PLL) to find the correct
word framing and issue bit slips to all 5 ISERDES if necessary.  And if for some reason one of the
5 ISERDES gets out of step with the other 4, how can you detect this?
 
My design instead used DDR input flops which then just loaded a set of 56-bit registers used like a
ring buffer.  This was roughly based on a Lattice 7:1 deserializer.  In their case a 4x gearbox input
was used instead of simple DDR.  The state logic that needs to run on the DDR input side is very
simple and should be no problem to meet timing in the S6.  It also runs nicely with just global
clock resources, no fancy clock buffers like the ISERDES - that was another place the documentation
was not very clear.  Again this was all for V5, and not S6 in my case.  Perhaps documentation has
gotten better since then.
 
-- Gabor
-- Gabor

我对BITSLIP的问题是同步多个通道以获得相同的滑动。
从数据表中不清楚BITSLIP是否会被重置。
Xilinx数据表和BITSLIP用户指南既不准确也不完整。
这一直是争论的焦点，尚未得到解决。
......基本上你说你可以复位所有的ISERDES（复位释放最好与位时钟同步 -  OUCH）然后使用其中一个ISERDES（连接到时钟输入，也可以转到
PLL）找到正确的字帧，并在必要时向所有5个ISERDES发出位滑动。
首先，有一个前提是BITSLIP被认为是Xilinx的“秘密酱”。
该功能的细节实现细节尚未公开，“功能描述”为模糊性留下了相当大的空间。
对于BITSLIP的Spartan-6版本尤其如此......但是在过去的论坛帖子中已经讨论过这个问题。
（Spartan-6）BITSLIP的框图既错误又不完整，因此几乎没有什么安慰。
话虽如此，BITSLIP是正在重置的功能。
如果重置其他任何东西，我们可能不在乎。
BITSLIP不是位时钟（或IOCLOCK）功能，它是字时钟功能。
此外，除非发出BITSLIP命令，否则RESET应该完全有效且足以为所有ISERDES块建立匹配和一致的BITSLIP状态 - 即使RESET的解除断言是异步的。
如果发出BITSLIP的逻辑保持安静，直到RESET被置位并取消置位，则RESET的目的将得到满足。
这些是我对Spartan-6（而非Virtex-6）背景下BITSLIP功能的理解和信念。
我不确定我对这个主题的第一线网页支持有信心 - 在过去提交给webcase的人们中，这个功能的技术“理解”存在冲突。
例如，Jonathan Heslip应该能够就此主题提供权威回应。
其他人尝试过并且（部分）失败了。
如果出于某种原因，5个ISERDES中的一个与其他4个ISERDES失去了一步，你怎么能发现这个？
对此没有简单的解决方案。
应该避免。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

The issue I had with BITSLIP was synchronizing the multiple channels to have the same slip.  It wasn't clear from the data sheet that the BITSLIP would be reset.
 
The Xilinx datasheets and user guides for BITSLIP are neither accurate nor complete.  This has been a past point of contention, and is yet unresolved.
 
... Basically you're saying that you can reset all of the ISERDES (release of reset had better be synchronous to the bit clock - OUCH) and then use one of the ISERDES (connected to the clock input, which also goes to the PLL) to find the correct word framing and issue bit slips to all 5 ISERDES if necessary.
 
First off, there is a premise that BITSLIP is considered Xilinx 'secret sauce'.  The nitty gritty implementation details for this function are not disclosed, and the 'functional description' leaves considerable room for ambiguity.  This is especially true for the Spartan-6 version of BITSLIP... but this has been discussed in past forum threads.  The block diagrams of (Spartan-6) BITSLIP are both incorrect and incomplete, so there is little comfort there.
 
Having said that, BITSLIP is the function which is being reset.  If anything else is reset, we probably do not care.  BITSLIP is not a bit-clock (or IOCLOCK) function, it is a word-clock function.
 
Furthermore, unless BITSLIP commands are being issued, then RESET should be completely effective and sufficient in establishing matching and consistent BITSLIP state for all the ISERDES blocks -- even if the de-assertion of RESET is asynchronous.  If the logic which issues BITSLIP is kept quiet until after RESET is asserted and de-asserted, the purposes of RESET will have been fulfilled.
 
These are my understandings and convictions for the BITSLIP function in the Spartan-6 (and not Virtex-6) context.   I am not sure that I would have confidence in first-line webcase support on this subject -- there have been conflicting technical 'understandings' of this function in past submissions to the webcase folks.  Jonathan Heslip, for example, is someone who should be able to offer an authoritative response on this subject.  Others have tried and (in part) failed.
 
And if for some reason one of the 5 ISERDES gets out of step with the other 4, how can you detect this?
 
There is no simple solution for this.  It should be avoided.
 
-- Bob Elkind
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首先，感谢gszakacs和eteam00的所有反馈
bassman59写道：
还有四个序列化数据对，而不是三个;
我认为这只是一个错字。
只是一个FYI-这不是一个错字，我使用LM98714和LM98725 AFE芯片，它们提供16位像素，因此只使用3个数据通道。
完整的数据表并未在线发布，但您仍然可以看到3个LVDS数据通道：
http://www.ti.com/product/lm98714
我还没有创建一个我完全满意的解决方案。
我没有花时间尝试使用IDDR，但我很快就会解决它。
然而，我确实花费了大量精力来使用SERDES并尝试使用CLOCK_DEDICATED_ROUTE约束，但在路由中收到了错误。
我会告诉你我是怎么做出来的。



以下为原文

First of all, thanks for all the feedback both gszakacs and eteam00

bassman59 wrote:

There are also four serialized data pairs, not three; I assume that's just a typo.

Just an FYI- this is not a typo, I am using a LM98714 and LM98725 AFE chips which give 16bit pixals so only 3 data channels are used. The full datasheet is not posted online but you can still see the 3 LVDS data channels:
 
http://www.ti.com/product/lm98714
 
I still have not created a solution I am completely happy with. I have not spend time trying to use IDDRs but I will get around to it soon. I did however spend a significant amount of effort on using SERDES and tried using CLOCK_DEDICATED_ROUTE constraint but recieved errors in routing.
 
I will let you know how I make out.