测量组合电路面积的最佳方法是什么

你读过这个帖子吗？
你和rex_nyu有同样的学校作业吗？
测量组合电路面积的最佳方法....，该区域是否以LUT表示？
1.如果您正在讨论FPGA而不是ASIC，您可以测量和比较*资源使用情况*，表示为“LUT数量”。
在同一主题上有很多论坛主题。
随意查找和阅读它们。
2.请不要将'LUT'作为面积测量值。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Have you read this thread?
 
Do you have the same school assignment as rex_nyu?
 
best way to measure the area of a combinatorial circuit...., would that area be expressed in LUT's?
 
1.  If you are discussing FPGAs rather than ASICs, you can measure and compare *resource usage* expressed as 'number of LUTs'.  There are many forum threads on this same subject.  Feel free to find and read them.
 
2.  Please don't refer to '# of LUTs' as an area measurement.
 
-- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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实际上，这不是一项学校作业。这是我的个人学习，更好地了解不同决策如何影响ISE工具的设计
因此，基于你的说法......比较不同设计方法对组合电路的资源利用率与LUT中表示的时序电路资源利用率的影响是否正确？
如果在Slice Registers中表达，或者是相同的事情？
问候，
亚历克斯



以下为原文

well actually is not a school assignment..It's for my personal study, to better understand how different decisions affect the design with the ISE tool
 
so therefore, based on your saying... It would be correct to compare the effects of different design methodologies on Resource utilization of a combinatorial circuit vs. Resource utilization of a sequential circuit expressed in LUTs?
 
or is the same thing if expressed in Slice Registers?
 
Regards,
Alex

为什么不根据寄存器和LUT进行比较？
不要忘记Block RAM和DSP48块。
一些设计和设计方法使用这些资源以及寄存器和LUT。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
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以下为原文

Why not compare based on both registers and LUTs?
 
And don't forget Block RAMs and DSP48 blocks.  Some designs and design approaches use these resources as well as registers and LUTs.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

因此......为了公平地表示一种方法或另一种方法对组合乘数面积的影响与对流水线乘法器面积的影响，需要将这种比较表示为LUTs与Slice寄存器？
或LUT与LUT？
简短的回答（至少对于FPGA来说 - 记住这是一个Xilinx论坛）是你的问题毫无意义。
FPGA通常具有逻辑元件，包括一个LUT加一个触发器以及一些额外的东西，如进位逻辑
可能有用也可能没用的多路复用器，具体取决于您使用的逻辑。
如果仅使用逻辑元件中的LUT，那么与使用相同的FPGA相比，您所占用的“区域”不会少
LUT及其相关寄存器。
因此，对于流水线与组合乘法器的情况，您应该这样做
发现每个最密集的版本将占用相同数量的逻辑元素，
除非您使用DSP48或MUL18x18等专用资源。
如果你想知道多少
每个设计区域都采用ASIC，然后找到适合所选择和测量的ASIC的综合工具
你的结果那样。
ASIC不会使用LUT作为门，也不会要求你浪费相邻的空间
在每个加法器阶段后不使用寄存器。
-  Gabor
-  Gabor



以下为原文

therefore....in order to make a fair representation of the effects of one methodology or another on the area of a combinatorial multiplier vs. effects on area of a pipelined multiplier would require to represent this comparison as LUTs vs Slice Registers? or LUTs vs LUTs?

The short answer (at least for FPGA's - remember that this is a Xilinx forum) is that your question makes no sense.
FPGA's typically have logic elements that consist of one LUT plus one flip-flop plus some extra stuff like carry logic
and multiplexers that may or may not be useful, depending on what you're using the logic for.
 
If you use just the LUT from a logic element, you take up no less "area" of the FPGA than using the same
LUT plus its associated register.  So for the case of pipelined vs. combinatorial multipliers, you should
find that the most densely packed versions of each will take up the same number of logic elements,
unless of course you use a dedicated resource like DSP48 or MUL18x18.  If you want to know how much
area each design takes in an ASIC, then find a synthesis tool which fits the ASIC of choice and measure
your results that way.  The ASIC won't use LUT's as gates nor will it require you to waste adjacent space when
not using a register after each adder stage.
 
-- Gabor
 
 
-- Gabor

我不是，我明白你的意思是：
因此，对于流水线与组合乘法器的情况，您应该发现每个最密集的版本将占用相同数量的逻辑元素，
......我相信逻辑元件的数量随着电路的类型而变化......例如，与3级流水线电路相比，组合电路将具有不同的资源利用率，而3级流水线电路的资源利用率与
一个5级流水线电路......
是我不确定你的意思....



以下为原文

I'm not shure I understand what you mean by:
 
So for the case of pipelined vs. combinatorial multipliers, you should find that the most densely packed versions of each will take up the same number of logic elements,
 
...I belive that the number of logic elements varies with the type of the circuit..... for example a combinatorial circuit would have different resource utilization compared to a 3 level pipelined circuit which in turn has different number of resource utilization compared to a 5 level pipelined circuit... 
 
is that I'm not sure what you mean....

每个（例如，spartan-6）切片包含4个寄存器和4个LUT。
消耗4个寄存器和4个LUT的设计模块可以跨越多达8个不同的片，或者可以打包到单个片中（取决于设计细节）。
根据片，寄存器，LUT或max [#LUT，＃registers]测量资源利用率将产生彼此不同的数字。
特别是，切片数量取决于映射和封装密度 - 除了设计的基本逻辑要求。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

Each (spartan-6, for example) slice contains 4 registers and 4 LUTs.  A design module consuming 4 registers and 4 LUTs could span as many as 8 different slices, or could be packed into a single slice (depending on design details).
 
Measuring resource utilisation in terms of slices, registers, LUTs, or max[ # LUTs, # registers ] will yield numbers which vary differently from one another.  In particular, the slices count depends on mapping and packing density -- in addition to the design's fundamental logic requirements.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

所以我看到这导致无处可去....你说没有有效的方法来比较同一电路在不同情况下的资源利用率？例如流动情况：...用寄存器实现时序电路
平衡：ON，然后使用寄存器平衡OFF实现相同的电路。那么这个特殊情况怎么样？
比较“Slice寄存器”中表示的两个电路之间的资源利用率是错误的？那么也许可以对LUT进行相同的比较？



以下为原文

so I see this leads towards nowhere ....You are saying that there is no effective way of comparing the resource utilisation of the same circuit in different situations?

Take for example the flowing case:
... a sequential circuit is implemented with Register Balancing: ON, then the same circuit is implemented with Register Balancing OFF.

So how about this particular case? comparing resource utilization between the two circuits expressed in "Slice Registers" would be wrong?

so maybe the same comparison can be made with LUTs?

以流动的情况为例：...使用寄存器平衡：ON实现时序电路，然后使用寄存器平衡OFF实现相同的电路。那么这个特殊情况怎么样？
比较“Slice寄存器”中表示的两个电路之间的资源利用率是不是错了？
我希望寄存器平衡不会改变设计中“Slice寄存器”的数量。
那会
意味着工具链中的东西被打破了。
它当然可以改变LUT的总数。
这一切
“寄存器平衡”的作用是在寄存器之前或之后移动（组合）逻辑，以便平衡
每个管道阶段的延迟。
例如，如果您将设计描述为两个带有两个的管道阶段
它们之间的逻辑层，输出后没有逻辑，寄存器平衡可能会移动一些逻辑
最后的输出阶段，以减少两个阶段之间的延迟。
在任何情况下，你都不能忽视LUT
顺序设计只是因为它也有触发器。
-  Gabor
-  Gabor



以下为原文


Take for example the flowing case:
... a sequential circuit is implemented with Register Balancing: ON, then the same circuit is implemented with Register Balancing OFF.

So how about this particular case? comparing resource utilization between the two circuits expressed in "Slice Registers" would be wrong?

I would hope that register balancing would not change the number of "Slice Registers" in the design.  That would
mean something is broken in the tool chain.  It certainly could change the overall number of LUTs.  All that
"Register Balancing" does is to move (combinatorial) logic before or after a register in order to balance the
delays in each pipeline stage.  For example if you have a design described as two pipeline stages with two
layers of logic between them, and no logic after the output, Register Balancing may move some logic after
the final output stage to reduce the delay between the two stages.  In any case, you can't ignore LUTs in
a sequential design just because it has flip-flops, too.
 
-- Gabor
-- Gabor

所以我看到这导致无处可去....你说没有有效的方法来比较不同情况下同一电路的资源利用率？
你完全误读了这个帖子中的帖子。
或者可能存在本地语言翻译问题。
以流动的情况为例：...使用寄存器平衡实现时序电路：ON，
然后使用寄存器平衡OFF实现相同的电路。那么这个特殊情况怎么样？
比较“Slice寄存器”中表示的两个电路之间的资源利用率是不是错了？
“切片寄存器”的比较可能对您有用且有用。
...可以用LUT进行比较？
是的，这是一个可能对您有用且有用的比较。
您需要确定哪些比较指标或指标对您很重要且有用。
每个FPGA都有有限数量的寄存器，IO引脚，LUT，互连等资源。
如果您受到寄存器而不是LUT的限制，那么仅基于LUT计数进行比较几乎没有意义。
您的FPGA设计还有什么？
你设计的其余部分是否会占用大量的寄存器？
您还需要了解所使用的FPGA系列的每个CLB或逻辑片中的资源。
对于每个Xilinx FPGA系列，它们都不相同。
继续努力，这并不复杂。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

so I see this leads towards nowhere ....You are saying that there is no effective way of comparing the resource utilisation of the same circuit in different situations?
 
You are completely mis-reading the posts in this thread.  Or possibly there is a native language translation problem.
 
Take for example the flowing case:
... a sequential circuit is implemented with Register Balancing: ON,
then the same circuit is implemented with Register Balancing OFF.

So how about this particular case? comparing resource utilization between the two circuits expressed in "Slice Registers" would be wrong?
 
Comparison of "Slice Registers" may be valid and useful for you.
 
... comparison can be made with LUTs?
 
Yes, that is one comparison which may be valid and useful for you.
 
You need to decide which comparison metric or metrics are important and useful to you.  Each FPGA has a limited number of registers, IO pins, LUTs, interconnect, etc. resources.  It makes little sense to compare based only on LUT count if you are limited by registers rather than LUTs.  What else is in your FPGA design?  Does the rest of your design gobble up lots and lots of registers?
 
You also need to understand the resources in each CLB or logic slice for the FPGA family you are using.  They aren't the same for every Xilinx FPGA family.
 
Keep working on this, it's not that complicated.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.