使用coolrunner 2 CPLD套件控制步进电机无法工作

PROCESS（clk，RESET，next_sreg，next_Q）
应该
过程（clk，RESET）
您声明了next_Q，但您没有声明Q.
dir是异步输入吗？
如果是这样，那么它需要与时钟clk同步，否则状态机逻辑*将被破坏并且状态机*将*挂起。
这是从最近的一个线程复制的问题的解释：
在下面的示例（Verilog）中，async_in输入信号将在不同时间传播到4位状态寄存器的输入。
这是因为互连延迟不匹配 - 并且它们无法匹配。
延迟不匹配可能超过纳秒。
如果在采样信号时发生async_in的转换，则各种状态机位将采样不同的async_in值的几率非常高。
如果至少一个状态位将看到'0'并且至少一个状态位看到'1'，则状态机将失败。
典型的症状是'锁定'。
输入时钟，async_in; reg [3..0] state = idle; reg edge_flag;
总是@（posedge clock）案例（州） 
idle：//等待异步输入async_in的低级别 
开始edge_flag if（async_in == 0）state end found_zero：if（async_in == 1）state found_edge：//找到上升沿，设置一个标志，循环回空闲状态 
开始edge_flag状态结束 
ENDCASE
在上面的示例中，解决方案是在状态机使用异步输入之前注册异步输入async_in。
这可确保状态机中的整个逻辑集以一致且均匀的输入信号运行。
你有模拟你的设计吗？
模拟是一个非常好的调试工具。
如果您的设计在模拟中不起作用，您可以获得对“破损”的了解。
如果您的设计在仿真中工作但在实际硬件中不起作用，那么可能出现的问题非常有限：
信号完整性问题与设备的输入或输出有关
时间裕度问题
电源问题
异步输入，处理不当
最后，Eilert的评论很明显（虽然他低估了异步输入对状态机的影响）。
输入DIR不仅要去抖动并与状态机时钟对齐，它也可能是低通滤波的。
一些步进电机在一个方向上继续时可以维持更高的步进频率，并且在来回踩踏时不能维持相同的高频。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。
在原帖中查看解决方案



以下为原文


should be


You declared next_Q, but you didn't declare Q
 
Is dir an asynchronous input?  If so, then it needs to be synchronised to clock clk, or the state machine logic *will* be corrupted and the state machine *will* hang.  Here is an explanation of the problem, copied from a recent thread:
 
In the example (Verilog) below, the async_in input signal will propagate through to the inputs of the 4 bits of state registers at different times.  This is because the interconnect delays are not matched -- and they cannot be matched.  The delay mis-match can be more than a nano-second.  If a transition of async_in occurs as the signal is being sampled, the odds are very very good that the various state machine bits will sample different values of async_in.  If at least one state bit will see a '0' and at least one state bit sees a '1', then the state machine will fail.  The typical symptom is 'lockup'.
 
input   clock, async_in;

reg   [3..0]  state = idle;
reg           edge_flag;

always @(posedge clock)
  case (state)

    idle:   // wait for a low level on asynchronous input async_in
      begin
        edge_flag <= 0;
        if (async_in == 0)  state <= found_zero;
      end
       
    found_zero:  if (async_in == 1)  state <= found_edge;

    found_edge:   // rising edge found, set a flag, loop back to idle state
      begin
        edge_flag <= 1;
        state <= idle;
      end
 
    endcase
 
In the above example, the solution is to register the asynchronous input async_in before it is used by the state machine.  This ensures that the entire set of logic in the state machine is operating with consistent and uniform input signals.
 
Have you simulated your design?  Simulation is a very good debugging tool.  If your design doesn't work in simulation, you gain some insight to what is 'broken'.  If your design works in simulation but doesn't work in actual hardware, there is a very limited set of likely problems at hand:

• signal integrity issues with an input or output from the device
  
• timing margin problem
  
• power supply problem
  
• asynchronous input which isn't handled properly
  

Finally, Eilert's comments are spot on (although he understates the consequences of async inputs to state machines).  Not only should the input DIR be debounced and aligned to the state machine clock, it might also be low-pass filtered.  Some stepper motors can sustain a higher step frequency when continuing in one direction, and cannot sustain the same high frequency when stepping back and forth.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.View solution in original post

PROCESS（clk，RESET，next_sreg，next_Q）
应该
过程（clk，RESET）
您声明了next_Q，但您没有声明Q.
dir是异步输入吗？
如果是这样，那么它需要与时钟clk同步，否则状态机逻辑*将被破坏并且状态机*将*挂起。
这是从最近的一个线程复制的问题的解释：
在下面的示例（Verilog）中，async_in输入信号将在不同时间传播到4位状态寄存器的输入。
这是因为互连延迟不匹配 - 并且它们无法匹配。
延迟不匹配可能超过纳秒。
如果在采样信号时发生async_in的转换，则各种状态机位将采样不同的async_in值的几率非常高。
如果至少一个状态位将看到'0'并且至少一个状态位看到'1'，则状态机将失败。
典型的症状是'锁定'。
输入时钟，async_in; reg [3..0] state = idle; reg edge_flag;
总是@（posedge clock）案例（州） 
idle：//等待异步输入async_in的低级别 
开始edge_flag if（async_in == 0）state end found_zero：if（async_in == 1）state found_edge：//找到上升沿，设置一个标志，循环回空闲状态 
开始edge_flag状态结束 
ENDCASE
在上面的示例中，解决方案是在状态机使用异步输入之前注册异步输入async_in。
这可确保状态机中的整个逻辑集以一致且均匀的输入信号运行。
你有模拟你的设计吗？
模拟是一个非常好的调试工具。
如果您的设计在模拟中不起作用，您可以获得对“破损”的了解。
如果您的设计在仿真中工作但在实际硬件中不起作用，那么可能出现的问题非常有限：
信号完整性问题与设备的输入或输出有关
时间裕度问题
电源问题
异步输入，处理不当
最后，Eilert的评论很明显（虽然他低估了异步输入对状态机的影响）。
输入DIR不仅要去抖动并与状态机时钟对齐，它也可能是低通滤波的。
一些步进电机在一个方向上继续时可以维持更高的步进频率，并且在来回踩踏时不能维持相同的高频。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文


should be


You declared next_Q, but you didn't declare Q
 
Is dir an asynchronous input?  If so, then it needs to be synchronised to clock clk, or the state machine logic *will* be corrupted and the state machine *will* hang.  Here is an explanation of the problem, copied from a recent thread:
 
In the example (Verilog) below, the async_in input signal will propagate through to the inputs of the 4 bits of state registers at different times.  This is because the interconnect delays are not matched -- and they cannot be matched.  The delay mis-match can be more than a nano-second.  If a transition of async_in occurs as the signal is being sampled, the odds are very very good that the various state machine bits will sample different values of async_in.  If at least one state bit will see a '0' and at least one state bit sees a '1', then the state machine will fail.  The typical symptom is 'lockup'.
 
input   clock, async_in;

reg   [3..0]  state = idle;
reg           edge_flag;

always @(posedge clock)
  case (state)

    idle:   // wait for a low level on asynchronous input async_in
      begin
        edge_flag <= 0;
        if (async_in == 0)  state <= found_zero;
      end
       
    found_zero:  if (async_in == 1)  state <= found_edge;

    found_edge:   // rising edge found, set a flag, loop back to idle state
      begin
        edge_flag <= 1;
        state <= idle;
      end
 
    endcase
 
In the above example, the solution is to register the asynchronous input async_in before it is used by the state machine.  This ensures that the entire set of logic in the state machine is operating with consistent and uniform input signals.
 
Have you simulated your design?  Simulation is a very good debugging tool.  If your design doesn't work in simulation, you gain some insight to what is 'broken'.  If your design works in simulation but doesn't work in actual hardware, there is a very limited set of likely problems at hand:

• signal integrity issues with an input or output from the device
  
• timing margin problem
  
• power supply problem
  
• asynchronous input which isn't handled properly
  

Finally, Eilert's comments are spot on (although he understates the consequences of async inputs to state machines).  Not only should the input DIR be debounced and aligned to the state machine clock, it might also be low-pass filtered.  Some stepper motors can sustain a higher step frequency when continuing in one direction, and cannot sustain the same high frequency when stepping back and forth.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我已经尝试过了，但是CPLD一直在等待第一个状态，我知道因为我将输出Q（3：0）分别发送到LED的ON位置69,69,66和64。
请看一下我写的新VHDL文件，实现过程中没有给出任何错误或警告。
half_step.vhd 3 KB



以下为原文

i've tried it again but the CPLD keeps waiting in the first state, i knew that because I sent the output Q(3:0) to the LED'S ON loc 69,69,66 and 64 respectively. please take a look at the new VHDL file i wrote, the implementation process didn't give any errors nor warnings.
            half_step.vhd ‏3 KB

感谢您的关注，但您知道我所知道的是如何使用VHDL编程，但我不明白您的异步输入是什么意思。
请解决我对此事的无知，并向我解释或给我一个建议的网站，我可以理解这一切。



以下为原文

thanks for the concern, but you know all i know is how to program in VHDL but i don't understand what you meant by an Asynchronous input. Please cope with my ignorance on this matter and explain it to me or give me a suggested site where i can understand all of this. 
 

非常感谢，我不认为单词可以表达我很好我觉得正确知道，确实dir是一个异步输入。



以下为原文

Thank you very much, i don't think words can be used to express i good i feel right know, Indeed dir is a was an asynchronous input.

你好。
你做过模拟吗？
结果是什么？
此外，如果您使用“当其他人=>”时您应该使用“null;”
背后的声明，并没有让这条线开放。
一些提示：
如果（hold ='1'）则state_motor else state_motor结束if;
这段代码很好，但太复杂，无法反映作为FF的CE信号的预期用途：
更简单的是：
if（hold ='0'）然后 - 保持充当not_ce state_motor结束if;
此外，现在电路仅在保持为“0”时才起作用。
SYNC_PROC灵敏度列表中不需要保持。
您仍然拥有异步输入目录，并且您的硬件在单一频率上运行。
但它并没有继续坚持在S0。
您是否提供了正确的重置序列并将保持拉低？
请创建一些测试平台并进行模拟。
有一个很好的模拟 
Eilert



以下为原文

Hi.
have you made a simulation? What are the results?
 
Also, if you are using "when others =>" you should use the "null;" statement behind it and not leave the line open.
Some hint:
if (hold='1') then
    state_motor <= state_motor;
else
    state_motor <= next_state_motor;
end if;
 
This code is fine, but too complex to reflect the intended use as a CE signal for the FFs:
simpler is:
if (hold='0') then  -- hold acting as not_ce
    state_motor <= next_state_motor;
end if;
Also it's more obvious now that the circuit works only when hold is '0'.
 
 
Hold is not needed in the SYNC_PROC sensitivity list.
You still have the asynchronous input dir and your hardware is running on a single frequency.
But it shoudn't keep stucking in S0.
Have you provided a proper reset sequence and pulled hold to low?
 
Please create some testbench and do a simulation.
 
Have a nice simulation
  Eilert