信号在fpga内部结构上运行的最大频率是？

嗨，
首先：
哪个FPGA系列？
该值由LUT和FF输出驱动器的上升和下降时间决定。
另一个限制因素是施加在驾驶员身上的负荷。
由于这在设计上有所不同，因此指定这样的值是没有用的。
您可以得到的是每个网络端点的延迟信息，例如
取自fpga_editor。
但延迟与通过电线传播的频率无关。
另一个问题是应该指定的最大时钟频率，至少对于DCM而言。
这对于高速优化的同步设计非常有用。
但实际达到此限制的设计（部件）很少。
静态时序分析可以告诉您特定设计的最大时钟频率和延迟（关键路径）。
有一个很好的综合 
Eilert



以下为原文

Hi,
first of all:
Which FPGA family?
 
This value is determined by the rise and fall times of the LUTs and FFs output drivers.
Another limiting factor is the load applied to the driver.
Since this varies from design to design, it would not be useful to specify such a value.
 
What you can get is a delay information for each net endpoint, e.g. taken from fpga_editor.
But delay has nothing to do with a frequency that travels over a wire.
 
Another thing is the maximum clock frequency, which should be specified, at least for the DCMs.
This is useful for highly speed optimized synchronous designs.
But there are only few design(parts) that actually reach this limit.
Static timing analysis can tell you about max clock frequencies and delays (critical path) of a specific design.
 
Have a nice synthesis
  Eilert
 
 
 

工作频率范围的共同点是全局时钟分配缓冲器的频率限制：BUFG。
在数据表中，查找BUFG缓冲区的最大频率。
你没有说你是否对学术论文或现实世界的设计感兴趣。
如果您对实际设计感兴趣，任何大于10个寄存器的系统都可能受到电路延迟和互连延迟的限制......但如果您是一名执业设计工程师，那么您已经知道了。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

A common denominator for operating frequency range is the frequency limit for the global clock distribution buffer:  BUFG.  In the datasheet, look for max frequency of the BUFG buffer.
 
You didn't say whether you interest is in the context of academic paper or real-world design.  If you are interested in a practical design, any system larger than 10 or so registers will likely be limited by both circuit delay and interconnect delay... but if you're a practicing design engineer, you already know this.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

它的斯巴达6。
是的，它由luts和ffs输出驱动器的上升和下降时间决定，也是由网络扇出。
我现在不关心延迟信息。
在fpga_editor中，值都是这个。
并且为全局网络指定了最大时钟频率信息，而不是针对一般结构。
理论是灰色的，只有生命之树永远！



以下为原文

its spartan 6. 
 
yes, its determined by the rise and fall times of the luts and ffs output drivers, also by the net fanout.
and i dont care the delay information now. in fpga_editor, the value is both of that.
 
and the maximum clock frequency information is specified for the global net, not for the general fabric.
Theory is grey,
and only the tree of life forever!

嗨，
是的，时钟网不是一般面料，但究竟什么是一般面料？
短线，长线，PIP互连，互连矩阵或这些的组合？
看起来您正在寻找一个不能由单个数字指定的值。
有一个很好的综合 
Eilert



以下为原文

Hi,
yes, the clock net is not the general fabric, but what exactly is the general fabric?
Short lines, long lines, PIP interconnects, interconnect matrices, or combinations of these?
 
It seems like you are looking for a value that can not be specified by a single number.
 
Have a nice synthesis
  Eilert
 

>并且为全局网络指定了最大时钟频率信息，而不是针对一般结构。
如果您对频率有所了解，那就意味着您有一个时钟用于您的设计。
您的设计时钟将位于其中一个专用时钟资源（BUFG全局时钟）上，此资源的最大频率将设置任何设计的上限。
设计的实际频率将由连接到时钟资源的两个同步资源（寄存器，BlockRAM，DSP等）之间的最坏情况路径设置。
如果你的设计只是一个寄存器到寄存器的路径，那么全局时钟将是限制因素，如果你在这两个点之间有30个逻辑电平，那么限制因素将是LUT和路由延迟，这只能由
实际上放置和路由您的设计。
注：如数据手册中所述，在某些模式下使用时，某些其他资源也可能在数据手册（DCM，PLL，BlockRAM，DSP，PCIe，MGT）中注明的最大频率限制低于BUFG限值
。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> and the maximum clock frequency information is specified for the global net, not for the general fabric.
 
If you are concerened about frequency then that means that you have a clock for your design.  The clock for your design will be on one of the dedicated clock resources (the BUFG global clock) and the maximum frequency for this resource will set the upper bound for any design. 
 
The actual frequency for your design will be set by the worst case path between two synchronous resources (registers, BlockRAMs, DSPs, etc) that are connected to the clock resource.  If your design is just a register-to-register path then the global clock will be the limiting factor, if you have 30 levels of logic between those two points then the limiting factor will be the LUT and routing delays that can only be determined by actually placing and routing your design.
 
Note: There some of the other resource may also have maximum frequency limits noted in the data sheet (DCM, PLL, BlockRAM, DSP, PCIe, MGTs) that are lower than the BUFG limit when used in certain modes as noted in the data sheet.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

嗨，eilert
即时寻找最坏的价值，无论什么样的一般面料。
理论是灰色的，只有生命之树永远！



以下为原文

hi, eilert
 

Theory is grey,
and only the tree of life forever!

嗨
例如，它只是我设计中的一个加号信号。
所以，我想知道加号的最小宽度可以在CLB之间的一般结构上传输，如短线，长线或低阻线。
顺便说一句，我不关心线路上的延迟。
理论是灰色的，只有生命之树永远！



以下为原文

hi
 
for example, its just a plus signal in my design.
so, i want to know the min width of the plus can be transmit on the general fabric between CLBs like the short line, long line, or lowskew line. by the way, i dont care about the delay on the line.
Theory is grey,
and only the tree of life forever!

嗨，
min的最坏情况值。
通过S6 FPGA的内部布线资源传输的信号的脉冲宽度。
好吧，也许Xilinx的某个人可以为你做一个SPICE .TRAN分析，除非你定义了什么限制了“最坏的情况”。
否则，一个migth使用单个IBUF并使用所有布线资源将其连接到所有切片输入。
这将是IBUF的最坏情况负荷。
如果您的要求是在驱动输入上也应识别信号，则这进一步限制了您的结果。
这个问题背后的意图是什么？
这个价值应该有什么用呢？
有一个很好的综合 
Eilert



以下为原文

Hi,
a worst case value for the min. pulse width of a signal traveling over the internal routing ressources of a S6 FPGA.
Well, maybe someone at Xilinx has fun to do a SPICE .TRAN analysis for you, unless you define what limits the "worst case".
Otherwise one migth use a single IBUF and connect it to all slice inputs using all wiring ressources. That would be the worstes worst case load for the IBUF. If your requirement is then that the signal should also be recognized on the driven inputs, this is further limiting your result.
 
What's the intention behind that question? What should this value be good for?
 
Have a nice synthesis
  Eilert

嗨
我只是想尝试异步逻辑。
问题是那个。
你对这个案子有什么建议吗？
谢谢。
理论是灰色的，只有生命之树永远！



以下为原文

hi



Theory is grey,
and only the tree of life forever!

我只是想尝试异步逻辑。
问题是那个。你对这个案子有什么建议吗？
1. Xilinx不支持异步设计
2.异步设计假设并要求无故障的组合门。
Xilinx LUT无法保证无故障。
建议：不要打扰。
基于SRAM的FPGA是涉及异步设计的错误技术。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

i just want to try asynchronous logic. the question is for that.
would u have any sugguestion for the case?
 
1.  Async design is not supported by Xilinx
 
2.  Async design assumes and requires glitchless combinatorial gates.  Xilinx LUTs are not guaranteed glitch-free.
 
Suggestion:  Don't bother.  SRAM-based FPGA is the wrong technology for dabbling in async design.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨，
你应该搜索论坛并阅读有关该主题的其他主题。
有关该主题的所有一般性问题都已在那里得到解答。
有一个很好的综合 
Eilert



以下为原文

Hi,
you should have searched the forum and read other threads on that topic.
all the general questions on that topic have been answered there.
 
Have a nice synthesis
  Eilert