数据统计不会改变

'wr_en'的断言不在图像上。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

The assertion of 'wr_en' is not on the image.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

断言是什么意思？
你的意思是将DEADBEEF插入FIFO吗？
非常感谢。



以下为原文

What do u mean by assertion?
 
Do u mean the insertion of DEADBEEF to the FIFO?
 
Thanks a lot.

“断言是什么意思？”信号处于活动状态，我预期为“1”。
这可能是在插入DEADBEEF时。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"What do you mean by assertion?"

The signal being at the active state, which I expect is  '1'. This is probably when DEADBEEF get inserted.
------------------------------------------
"If it don't work in simulation, it won't work on the board."

仅当WR_EN置为有效（高电平）时，才将数据写入FIFO。
如果数据未写入FIFO，则数据计数不会更改。
这在FIFO IP数据表中有详细说明。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Data is written to the FIFO only when WR_EN is asserted (high).
If data is not written to the FIFO, the data count won't change.
This is spelled out in the FIFO IP datasheet.
 
-- Bob Elkind
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但是，如果我从Fifo读取，那么数据计数不应该减少吗？
非常感谢。



以下为原文

But if I read from the Fifo, shouldn't the Data count decrement?
 
Thanks a lot.

这是wr_en的断言：
http://imageshack.us/photo/my-images/155/56900884.jpg/
有线。
当我插入另一个单词时，数据计数变为2，当我读到时，它会回到1，但由于某种原因，它不会回到零...



以下为原文

Here is the assertion of the wr_en:
 
 
http://imageshack.us/photo/my-images/155/56900884.jpg/
 
 
wired.
 
When I insert another word, the data count goes to 2, and when I read, it goes back to 1, but from some reason, it doesn't go back to zero...

您要定位哪个FPGA器件系列？
您使用的是什么版本的ISE？
您使用的是ISE综合或第三方综合工具吗？
你的FIFO有多深？
你用RESET初始化FIFO吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

Which FPGA device family are you targeting?
What version of ISE are you using?
Are you using the ISE synthesis, or a 3rd party synthesis tool?
How deep is your FIFO?
Do you init the FIFO with RESET?
 
-- Bob Elkind
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奇怪的是，当您写入FIFO时，EMPTY标志变为低电平。
在实际发生READ之前，EMPTY标志在RD_EN被置位的相同时钟周期内返回HIGH。
我怀疑你的模拟信号集是不完整的。
请发布您的FIFO代码，值得检查。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Odd, when you write to the FIFO, the EMPTY flag goes low.
The EMPTY flag returns HIGH in the same clock cycle that RD_EN is asserted, before the READ has actually taken place.
 
I suspect your simulation signal set is incomplete.  Please post your FIFO code, it's worth checking.
 
-- Bob Elkind
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嗯......我确信Xilinx设计人员社区的战马对Xilinx FIFO的细节和异国情调非常熟悉。
不幸的是，我不像其他人那样知识渊博。
见UG175，表5-5。
这表示当FIFO为空（或接近空？）时，DATA_COUNT输出不准确。
作为设计人员，这表明必须使用EMPTY标志来指示FIFO_empty条件，并且不应将DATA_COUNT输出用于FIFO_empty信令。
每天学些新东西！
- 鲍勃埃尔金德
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以下为原文

Hmmm...  I'm sure the warhorses of the Xilinx designers community are utterly familiar with the details and exotic behaviour of the Xilinx FIFOs.  Unfortunately, I am not as knowledgeable as others.
 
See UG175, Table 5-5.  This indicates that the DATA_COUNT output is not accurate when the FIFO is empty (or near empty?).  As a designer, this suggests that the EMPTY flag must be used to indicate the FIFO_empty condition, and the DATA_COUNT output should not be used for FIFO_empty signaling.
 
Learn something new, every day!
 
-- Bob Elkind
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是的，事情是我想使用数据计数状态，告诉CPU在Fifo中的项目数...
没关系，我想我会用一个柜台或什么......
非常感谢。



以下为原文

Yeah, the thing is I wanted to use the Data count for the status, to tell the CPU the number of items in the Fifo...
 
Never mind, I guess I'll use a counter or something...
 
Thanks a lot.

另外需要注意的是，行为模型并不完全准确，因此您应该使用结构模型。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

The other thing to note is that the Behavioural models are not entirely accurate, so you should use Structural models.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

您还应该在核心生成器中使用“使用额外逻辑进行精确计数”选项。
据我所知，除了rcingham关于使用结构模拟模型的评论之外，这可能会解决您的问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

You should also use the 'use extra logic for accurate count' option in the core generator.  For all I know, that might fix your problem -- in addition to rcingham's comment about using the structural sim model.
 
-- Bob Elkind
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鲍勃的最后一个答案是现场。
准确的数据计数有两个要求
从最新版本的FIFO生成器：
1）将数据计数信号的宽度定义为其最大值。
2）选择Bob所指出的“额外逻辑”复选框。
而且，行为模型非常破碎。
除了不“循环准确”
它没有正确建模FIFO的所有可选标志。
简单地说，不要使用它。
总而言之，使用数据计数输出确定FIFO是否是一个坏主意
空。
只保证空旗准确。
而“额外的逻辑”将导致
数据计数变为零，它不一定会在空标志的同一循环中这样做
断言。
最后，您应该知道所有Xilinx Coregen FIFO都支持读写
内部空或满状态。
因此，写入完整FIFO或读取空FIFO没有
影响。
问候，
的Gabor
-  Gabor



以下为原文

Bob's last answer is spot-on.  There are two requirements for an accurate data count
from recent versions of FIFO generator:
 
1) Define the width of the data count signal to its maximum value.
2) Select the "extra logic" checkbox as noted by Bob.
 
Also, the behavioral model is extremely broken.  In addition to not being "cycle accurate"
it doesn't properly model all of the optional flags of the FIFO.  Simply put, don't use it.
 
All that being said, it's a bad idea to use the data count output to determine if the FIFO is
empty.  Only the empty flag is guaranteed accurate.  While the "extra logic" will cause the
data count to go to zero, it won't necessarily do so on the same cycle that the empty flag
asserts.
 
Finally you should be aware that all Xilinx Coregen FIFO's gate the read and write enable with
the internal empty or full condition.  Thus writing a full FIFO or reading an empty FIFO has no
effect.
 
Regards,
Gabor
-- Gabor

我觉得他需要牛排配方



以下为原文

I think he needs the recipe for steak
 

嘿。
首先，谢谢你们的答案。
1）我将Fifo设置为64写入深度，默认情况下它给了我7位数据计数宽度，虽然我不知道，6就足够了。
在FIFO宽度深度附近，它表示实际宽度深度：66，也许这就是它给我7位宽的原因？
2）“额外逻辑”已标记在灰色框中，我甚至无法更改它。
“行为模式极度破碎”是什么意思？
你怎么能从图片中看到它？
我没有中断数据计数来检查FIFO是空还是满，但我需要将该值返回给CPU（项目的一部分）。
非常感谢。
阿萨夫。



以下为原文

Hey.
 
First of all, Thanks for the answers guys.
 
1) I set the  Fifo to 64 write depth, by default it gave me 7 bit data count width, I don't know way though, 6 is sufficient. Near the FIFO width depth it says actual width depth: 66, maybe this is the reason it gives me 7 bit width?
 
2) the "extra logic" is already marked in grey box, I can't even change it.
 
What do u mean by "the behavioral model is extremely broken"? How can u see it from the pic?
 
I'm not relaying on the data count to check if the FIFO is empty or full, but I need to return that value to the CPU (part of the project).
 
Thanks a lot.
Assaf.

“我不依赖于数据计数来检查FIFO是空的还是满的，但我需要将该值返回给CPU（项目的一部分）。”在这种情况下，您应该自己计算。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"I'm not relying on the data count to check if the FIFO is empty or full, but I need to return that value to the CPU (part of the project)."

In which case you should count it yourself.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

1）我将Fifo设置为64写入深度，默认情况下它给了我7位数据计数宽度，虽然我不知道，6就足够了。
在FIFO宽度深度附近，它表示实际宽度深度：66，也许这就是它给我7位宽的原因？
这也是它的一部分，即使实际最大深度为64，你需要7位代表来自的值
0（空）到64（完整）。
6位只能使您从0到63.在任何情况下，如果您不使用最大值
深度输出中的位数，核心将尝试缩放输出以适应。
所以你会得到的
除了FIFO中的实际字数之外的其他内容。
“行为模式极度破碎”是什么意思？
你怎么能从图片中看到它？
我根据自己对模型的经验说这个。
在我的情况下，我几乎可以编程
和可编程的几乎空标志，这些标志在行为模型中根本就没有断言。
它
似乎新一代的行为模型没有正确更新
FIFO出现了（具有第一个字落入和可编程标志的版本）。
顺便说一句，如果这是一个“异步”FIFO，即独立的写和读时钟，你想要
使用读取FIFO的一侧读取数据计数，而不是写入数据计数。
而两个
当一切都处于静止状态时，计数应该匹配，读取数据计数是同步的
读取时钟和“保守读取”意味着它永远不会显示比实际更多的数据
在FIFO中。
写数据计数与写时钟同步，并且是“保守的”
写作“意味着它永远不会显示比FIFO中实际可用的更多空间。
-  Gabor
-  Gabor



以下为原文

 
1) I set the  Fifo to 64 write depth, by default it gave me 7 bit data count width, I don't know way though, 6 is sufficient. Near the FIFO width depth it says actual width depth: 66, maybe this is the reason it gives me 7 bit width?
 
That's part of it, also even if the actual max depth is 64 you need seven bits to represent the values from
0 (empty) to 64 (full).  6 bits only gets you from 0 to 63.  In any case if you don't use the maximum
number of bits in your depth output, the core will attempt to scale the output to fit.  So you will get
something other than the actual number of words in the FIFO.
 
What do u mean by "the behavioral model is extremely broken"? How can u see it from the pic?
 
I say this from my own experience with the models.  In my case I had programmable almost-full
and programmable almost-empty flags that simply never asserted in the behavioral model.  It
appears that the behavioral models were not updated properly when the newer generation of
FIFO's came out (versions with first-word fall-through and programmable flags).
 
By the way, if this is an "asynchronous" FIFO, i.e. independent write and read clocks, you want to
use the read data count from the side reading the FIFO, not the write data count.  While the two
counts should match when everything is quiescent, the read data count is synchronous to
the read clock and "conservative for reading" meaning it never shows more data than is actually
in the FIFO.  The write data count is synchronous to the write clock and is "conservative for
writing" meaning it never shows more room than is actually available in the FIFO.
 
-- Gabor
-- Gabor