完善资料让更多小伙伴认识你，还能领取20积分哦， 立即完善>
3天内不再提示
电子发烧友论坛|
新设计从旧设计升级......基本上Dout不会发生。
这是因为（我猜）在EEPROM芯片内部的复位极性是错误的。我已经仔细检查过字节0x2000是0x00而数据+字节2000校验和是否与100％工作的主金板匹配.. OE / 从4010和CClk复位是正确的.4010复位延迟正确@ 64 mS-我可以在示波器上看到。 Clk是1uS-正确的。 如果我从4010断开OE /复位并将其连接到地面， 然后EEPROM将输出数据...... 从逻辑上讲，这告诉我OE /复位极性仍未正确编程。 最初，字节2000设置为0xFF（仍然没有工作）所以我虽然重新编程为0x00将解决问题，但它没有。 有没有人遇到过这个问题？ 老帽子，我知道，但它是一个重要的传统航空航天设计，所以没有机会使用最新的东西:)除了，可能用最新的闪存部件取代17V16。 17V16的PLCC是众所周知的母鸡:) tiA 以上来自于谷歌翻译 以下为原文 New board design upgrade from old design... Basically the Dout doesn't happen. That's because ( I'm guessing) that the reset polarity is wrong inside the EEPROM chip.I've double checked that byte 0x2000 is 0x00 and the data +byte 2000 checksum matches the master gold board which is working 100%..OE/reset from the 4010 and CClk are correct.The 4010 reset delay is correct @ 64 mS- I can see that on the scope. Clk is 1uS- correct. If I disconnect OE/reset from the 4010 and connect it to ground,. then the EEPROM will output data... Logically, this tells me that the OE/reset polarity is still not correctly programmed. Initially, byte 2000 was set at 0xFF ( still didn't work) so I though that reprogramming to 0x00 would fix the problem, but it hasn't. Has anyone come across this issue before ? Old hat, I know, but it's an important legacy aerospace design, so no chance of using the latest stuff :) Except, maybe replacing the 17V16 with the latest flash part. The 17V16's PLCC are the proverbial hen's teeth :) TIA 
0
|
|
相关推荐
4个回答
|
|
|
顺便提一下，我的解决方案是在子板上安装Atmel AT Mega32 QFN，将4010重新配置为Slave串口并从SPI输出配置数据32.Plenty足够快，pcb将直接焊接到44PLCC封装垫:)
聪明，但没有机会...... 以上来自于谷歌翻译 以下为原文 Incidentally, my solution would be an Atmel AT Mega32 QFN on a daughterboard, reconfigure the 4010 to Slave serial and have the 32 pump out config data out of SPI.Plenty fast enough and the pcb would solder directly to the 44PLCC footprint pads :) Smart, but no chance.... |
|
|
|
|
|
除非您购买的17V16版本严格用于Altera FPGA
那么我认为复位极性应该是可编程的。 自从我使用4000以来已经很久了 系列部件和17xxx EPROM，但我记得，为PROM创建的.mcs文件没有 包含复位极性开关。 您必须在编程选项中设置复位极性 您的编程系统。 我们当时使用的是BP1200程序员，但我愿意 期望任何支持该部件的程序员都应该在设置中有选项 某处。 HTH， 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 Unless you bought a version of the 17V16 that was strictly intended to work with Altera FPGA's then I think the reset polarity should be programmable. It's been a long time since I used 4000 series parts and 17xxx EPROMs, but as I recall, the .mcs file created for the PROM did not contain the reset polarity switch. You had to set the reset polarity in the programming options of your programming system. We used a BP1200 programmer at the time, but I would expect any programmer that supports the part should have the options in the settings somewhere. HTH, Gabor -- Gabor |
|
|
|
|
|
有意思的是，从来不知道有17V16部件没有重置电源......我绝对可以写入2000，在编程器中重置字节2000（DataI / O 3980）然后读回舞会并看到字节2000是00（改为
FF）。 以上来自于谷歌翻译 以下为原文 Interesting, never knew there was 17V16 parts with no reset poilarity.... I can definitely write to 2000, reset the byte 2000 in the programnmer (DataI/O 3980) then read back the prom and see byte 2000 is 00 ( changed from FF). |
|
|
|
|
|
就像我说我用这些部件已经好几年了，所以它可能是一些东西
除17Vxx系列外，具有固定的良性。 我记得的是极性位 未存储在Xilinx工具为PROM准备的.mcs文件中。 我不得不打开 BP编程软件中的单独选项对话框，以正确设置极性， 我还记得极性（重置低电平有效）不是默认值 - 所以如果我忘了 设置部件不起作用。 我记得那些部件不可重新编程，所以 你真的很想第一次就把它弄好。 问候， 的Gabor - Gabor 以上来自于谷歌翻译 以下为原文 Like I said it's been years since I played with these parts, so It may have been something other than 17Vxx series with the fixed polrity. What I do remember is that the polarity bit was not stored in the .mcs file prepared for the PROM by the Xilinx tools. I had to open up a separate options dialog in the BP programming software to set the polarity properly, and I also remember that the polarity (Reset active low) was not the default - so if I forgot to set it up the parts didn't work. As I recall those parts were not re-programmable, so you really wanted to get it right the first time. Regards, Gabor -- Gabor |
|
|
|
|
只有小组成员才能发言，加入小组>>
2370 浏览 7 评论
2789 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办？
2257 浏览 9 评论
3331 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区？
2420 浏览 15 评论
有输入，但是LVDS_25的FPGA内部接收不到数据，为什么？
743浏览 1评论
请问vc707的电源线是如何连接的，我这边可能出现了缺失元件的情况导致无法供电
531浏览 1评论
求一块XILINX开发板KC705，VC707，KC105和KCU1500
348浏览 1评论
748浏览 0评论
1950浏览 0评论
/7 
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 （电路图） 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证：合字B2-20210191
工商网监
湘ICP备2023018690号
2174
评论
淘帖
290
